You need a transistor model that captures NBTI.

From an extracted SRAM layout you can then do spice-like simulations using the model. It will work. You probably will have to size the SRAM accordingly, probably only a few bits, otherwise your simulation will take a long time to complete.

Best case is obviously to have additional pass gates so you can isolate each transistor and do a characterization post stress - however I assume you are stuck with a standard 6T SRAM and are asking how the Vt shift induced by NBTI can be inferred.

I think the NBTI or other Vt shift will affect the shape of the SRAM stability curve (Static Noise Margin or Butterfly curve).  If NBTI is a dominant effect then, along with a calibrated SPICE model of the p and n transistors you should be able to extract an equivalent Vt shift from NBTI that is causing the shift in the SNM curve.  It will be a recursive hand operation in the sense that some trial and error will be need to reproduce the SNM curves from the SPICE SRAM cell model as a function of Vt shift on the transistors.  

Thank you both, @Samuel Pagliarini @ Robert C.Baumann. I have measured the NMOS PBTI effect  in SOI technology, and the Vth shift of 10 mv recently at 30000s. I think the PMOS will be worse and i will do it to check out that, then put the result here. One more questions, If i want to change the Vth, it is enough for me fix the Vth0 in spice model file? or fix any other parameters? 

Thank you!