In order to evaluate the area needed for the two circuits, you need a layout view of the circuits (custom layout or automatic place-and-route need to be done). From the layout, the silicon area occupancy for the circuits can be immediately measured taking the dimensions of a bounding box including the cells (you can use the rulers in Cadence to measure distances).

If a layout view is not available and your circuit is a pure-digital design based on standard cells, an estimate of area occupancy can be obtained summing the area of the cells included in it, plus an overhead to account for the area needed for interconnects (it depends on the target technology (#of metal layer) and on the interconnect density of your design). Obviously, what you get is an approximate estimate. If your circuit includes relevant analog/mixed-signal or full-custom parts, even though the drawn dimensions of the primitive cells included in it are known, the last approach is not valid unless a very coarse estimate is sufficient, since analog/mixed-signal layout generation is not a systematic process.

You can transfer the netlist on your design to design vision and calculate area power delay

The area can't be estimated from the design until you go through the layout.

You have to layout your circuit then you can measure the dimension of the chip using the ruler.

Dear Ashish,

If you have designed an analog circuit you need to draw your circuit's layout and measure it simply using the ruler. In some cases you have to take into account the area reserved for the pads as well. For digital circuits I am not sure whether it is possible or not to have an estimate of the circuit area before drawing the layout. If your circuit is fully based on standard cells you could maybe check the cells area and make a gross estimate. Consider some margin for interconnection.

Best,

Gabriel  

Hello,

how to calculate delay, power consumption, and area of a circuit using Hspice?