Hello all,
I need to fabricate a working solar cell (thin film 100 nm Si) preferably in vertical architecture (later architecture can also be done). I have SOI wafer with 300 nm SOI layer (lightly p doped , resistivity of 500 ohm/cm), 3 um buried oxide and then Si handle wafer. I usually thin down the SOI layer by dry oxidation and etching to 100 nm. For my work, I need to lower Si absorption as much as possible. However, I tried to fabricate a vertical p-n junction but my diodes doesn't show good diode behavior. One important thing to note is that the devices have all top contact. 1 chip has 7 devices of 1.5 mm x 1.5 mm, but only one common contact to the p-doped SOI (7 devices have individual 7 top contacts on n-doped layer). However, the common contact is approx. 3 mm-10 mm away depending on the device that is being measured. My understanding is that this way of making common contact is very bad. If anyone has any suggestion please let me know.
Thanks
I have some experience making UV photodiodes in SOI material and a lot of experience making high efficiency III-V solar cells.
My first comment is that with only a 100 to 300 nm absorption layer, the quantum efficiency and therefore the short circuit photocurrent will be quite poor no matter what you do.
The second comment is that since the material has such a high sheet resistance (500 ohm cm / 100*1e-7cm) or 50Megoms/square the series resistance to your commpon P type contact is likely dominating the IV curve resulting in low efficiency.
Since you do not describe how you are making a junction for your cell, it is hard to comment further on you current approach. Bellow I describe what I would do in this situation. You are welcome to use it if you think it a good idea.
Given the high series resistance, my best advice would be to make a cell with interdigitated metal contact fingers, (like if you put the fingers of your two hands between each other) with one set of fingers the ohmic contacts to the P material (e.g. alloyed Al), and the second set of fingers a Schottky barrier to the P-material.(e.g. TiPtAu). The ohmic metal should be done first and annealed before depositing the Schottky contact material. The Schottky contact is not as good as a PN junction in terms of dark current and Voc, but you will not have to worry about diffusion or implantation depth in the thin Si. The gap between the sets of interdigitated fingers needs to be as wide as possible to reduce shadow loss but no wider than the depletion region around the Schottky, which extends laterally as well as underneath the metal. This gap needs to be depleted so that the light incident between the pairs of fingers generates the electron-hole pairs (what few can be generated in the 100nm thick Si) that can be accelerated in the high field in the depletion region, generating the current. The 500 ohm-cm Si is a doping of about 3e13/cm3 P type, so the zero-bias depletion region will be very roughly 10 microns or so. Therefore you want both sets of metal fingers to be as narrow as you can make (1 um wide if possible) to reduce shadow (light reflection) loss with about a 10 um gap. he fingres should connect to whatever the minimum pad size you need is. Remember on the Schottky side this pad is also a junction area, that contributes dark current but no useful light collection, so make it as small as possible. A single layer AR coating of PECVD SiN may increase the photocurrent add about 30%. Dont forget to open up vias over the contact pads. Good luck...
Regards,
Steven Wojtczuk, Ph.D.
Senior Scientist
Masimo Semiconductor
Hello Dr. Wojtczuk
I really appreciate your very thoughtful and through answers on my questions. All of your suggestion make sense to me and I am really excited to get your feedback. In the meantime, I was also looking for MIS type solar cell architecture to avoid problems associated with fabricating p-n junction on thin Si layers. So far I have tried to make a p-n junction using spin on dopant and rapid thermal annealing to achieve a shallow junction. But I think I have no definite control on the process, as I have no facility to run SIMS on the samples, thus I have no idea about the junction depth. So after several trials I understood that I will not get a active solar cell with such guess works and started looking for some other structures that can give me an working solar cell (for my case I am not looking to maximize the efficiency but will use the system as a proof of concept test structure) without the complexity associated with doping thin Si film. Thus I started looking on the MIS type solar cell structure. But I was not sure on how to proceed on that given I have a high resistivity p-type substrate. I was becoming very confused on how to place the contacts on the substrate. Your answer and suggestion is extremely helpful in that regard. I was also thinking that may be I can deposit intrinsic and n-doped polySi layers (as cheap but not efficient option) on top of the p-layer and achieve a junction after annealing. But I didn't get a chance to try it as the LPCVD is down for several weeks. In any case, I am very thankful to your suggesting and letting me try it.
Thanks
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