You can find it here: 

http://www.cerc.utexas.edu/~jiwoo/vlsi1/lab1/cadence_tutorial

The title is Logic simulation with Verilog-XL

Extract your design in virtuoso and generate a spice netlist. Using any simulator capable of handling mixed language simulation should work.

Here is a tutorial showing how to do it using spectreVerilog: 

http://www.seas.gwu.edu/~vlsi/ece126/FALL/labs_tutorials/lab9_stimulus_verilog_inverter.pdf