I am simulating the breakdown of a si vdmos, when it reaches the breakdown, the progorm gets Non convergence with the increasing drain voltage, so I try to increase the current of drain useing the following codes, but the progrom gets convergence, but I-V cure goes back with the increasing drain current, I dont know the reason, does anyone have met the similiar issues?
models srh fldmob surfmob auger
impact selb
contact name=gate n.polysilicon
interface qf=3e10
solve init
method newton trap maxtraps=10 climit=1e-4 ir.tol=1e-30 ix.tol=1e-30
log outf=VDMOSFET_BR.log
solve vdrain=0.1
solve vdrain=1
solve vdrain=10
solve name=drain vstep=2 vfinal=52
solve vstep=0.1 vfinal=52.5 name=drain compl=1.e-2 cname=drain
contact name=drain current
solve previous
solve istep=1.2 imult ifinal=1e-03 name=drain previous
I think this is avalanche breakdown.
What basically happens :
1. Breakdown starts.
2. The mobility carriers (electrons/holes) move very rapidely in the crystal lattice as a result of the high electrical fields.
3. They then hit other atoms with great energy, the result of this is that electons jump from the valence band to the conduction band, creating electron/hole pairs, sustaining the avalanche.
4. As a result of the effect the breakdown cure goes back.
Regards,
Henri
I agree with Henri Cloetens, it seems only that you reach avalanche/breakdown process above 50 V (which look usual). However, it in not easy to understand where it comme from in your simulation/model ... it seems that you share us some parameters of the simulation ... but not the model of the VDMOS itself ?
Curiosity : The name of the simulation using "BR" (like BReak?) look like it is precisely the "breakdown" which is considered ?
And why is there a ".log" in the title, is there any log scale somewhere ?
Any way, you can find a similar ID(VDS) characteristics in the paper discussion high voltage MOS transistors :
A. Tanaka et al 2010 Modeling of 2D Bias Control in Overlap Regionof High-Voltage MOSFETs for AccurateDevice/Circuit Performance Prediction
Fig 10 : Conference Paper Modeling of 2D bias control in overlap region of high-voltag...
Regards
Damien PRÊLE
Dear Justin,
At first Good Work! The breakdown C/Cs is a very tedious job not only in VDMOS but any semiconductor device, specifically with negative resistance, as I can see in your graph. You'd get acquainted with the Continuity Methods and how to use it as a solution method in SDevice.
https://www.researchgate.net/project/Modeling-Numerical-Simulation-of-all-Semiconductor-Devices
Henri Cloetens Thanks so much for answering. But I didn't quite get your idea. Indeed, the "go back" happens at the point of breakdown voltage, and you describe the process of avalanche breakdown in detail，but for normal sistuations, as the breakdown happens, the I-V cure should just goes up sharply, right? I still don't understand why it goes back. Thanks.
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