Dear Marzieh,

I do not know how do you exactly calculate the Cds, but according to its definition Cds= d QDS/ dVDS, so it is the small signal capacitance between the drain and the source. QDS is the large signal charge between the drain and source and VDS is the applied large signal voltage. If QDS versus VDS is such that QDS decreases with increasing VDS , the calculated capacitance will be negative. So, to verify this result you need to calculate QDS versus VDS.

Best wishes

Interesting

It is not clear how you calculated the capacitance. You might have calculated impedance instead. One way to check is to change frequency or bias conditions and check the behavior.

From your question I think you are interested in Device Circuit co-design (Device simulation in silvaco) and (Circuit simulation in ADS). You can directly do the S-parameters simulation in silvaco (Download the file from input deck ... https://www.silvaco.com/examples/tcad/section32/example2/index.html) and put those data in the ADS tool (For importing S-parameters https://www.youtube.com/watch?v=ehmDhLn0Bm8).

Thanks very much for your answer. I looked into the input deck you sent me the link and the code line for ac simulation. It was exactly what I used in my simulation to obtain the capacitances Cgs, Cds, and Cgd.

Ac.analysis sparam . . .

But the problem is that this code line must be used only for small signal and I need to obtain these capacitances for large values of drain voltage to see how they vary with bias. However I have used the same code line for large values of drain voltage and the capacitances Cgs and Cgd are obtained having the expected variation with the bias though I'm not sure if I have chosen the right approach. The problem is that only the value of Cds is negative and I don't how to obtain it because I need its value in the nonlinear model I have developed in ADS.

I would definitely appreciate any suggestions or recommendations of yours on this issue.

Best regards,

Mahrokh

The negative Cds can be considered as an inductive effect below resonant frequency. The elctrical equivalent model may not be taking any capacitive or inductive effect in consideration at that terminal of the transistor

An easy and traditional way to get an accurate value of Cds is to measure or download the S parameters of the device under test (DUT) at different frequencies ( e.g : from 1 GHz to 20 GHz ) then using the de-embedded technique to determine the equivalent circuit parameters of the DUT ( small signal model) using an optimization algorithm.