Dear Subhashree,
in order to design the 6-T SRAM you have to consider the write and read operation. The read operation must not destroy a a logic one written in the cell. Also in the write operation of zero must be enabled. To make the pull up time and the pull down of the the CMOS inverters symmetrical the w/l ratio of the p-MOS transistors must be about 3 times that of the nmos. Otherwise the transistors must be of minimum w/L ratio.
For a sizing tutorial please follow the link:https://engineering.purdue.edu/~vlsi/ECE559_Fall09/HW/HW6_Solution.pdf
Best wishes
You do the Size variation. change the width of two transistors (which are connected to bit lines) and do analysis. Use a good sense amplifier to get perfect output.
when I was doing my project i m nt getting the perfect o/p.if u want then u can flow the raw data of my thesis and i hv a pdf also which may be usefull for u
for high-density cell
-> pulldown (PD) should of minimum size.
-> pass gate (PG) should be between 1-1.5 times of PD
->pullup (PU) should be around 0.7-0.8 times of PG.
in general start with the sizing of the PD and size PG and PU accordingly as defined above.
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