4 Questions 9 Answers 0 Followers
Questions related from Telajala Venkata Mahendra
Dear all, How to calculate setup time and hold time of a memory circuit in CADENCE Spectre Simulator?. We have designed Content Addressable Memory (CAM) using 45 nm technology in CADENCE Spectre...
06 January 2020 9,724 3 View
Dear all, I am requesting you all to give me answer/reason for the following question? Why static power increases with the increment of temperature in CMOS memory circuits or CMOS circuits? What...
04 November 2019 9,118 4 View
I simulated a CMOS design using 45 nm technology. With increase in supply voltage there is a gradual increment in delay has been observed? why the delay is increased with increment of supply...
01 December 2016 4,290 4 View
I simulated a CMOS design in 45 nm technology by varying the temperature. The power and delay is affected by temperature. why it happens? what is the reason behind it.
01 December 2016 7,200 4 View