During BEoL via patterning, arcing is observed sometimes to the point of wafer breakage(seal band arcing). Failure analyses show craters at the point of the arcing. These craters appear at other times as well without resulting in wafer breakage. This is most often during the via etch or Ash step in the etch chamber. What could be the root cause of this?
Hi.
It is usually caused by charge accumulation on layers or surfaces that cannot evacuate them as quickly as they accumulate...leading thus to arcing in between two differently charged areas. Charging is due to plasma...and depends mainly on source power and bias polarization.
Regards.Mohamed.
Depending on the etcher you are using, you may be able to reduce charge accumulation by connecting the top of your wafer to the chuck with conductive tape.
Connecting the wafer to the chuck with a tape might be difficult in this case because the etcher is a CCP production tool and it would definitely be an effort to tape all wafers one by one to the chuck.
Maybe you could put the tape around the edge of the wafer to provide some continuity to the back side. What is the model of the etcher.
Its a TEL product..capacitively coupled plasma chamber. What about reaction of the plasma with the tape and the defects it may probably introduce from the byproducts?
Use a metal tape or a carbon tape to match the chemistry of your etch. Gold foil or silver paint could also be options. The main thing is that you need to prevent the charge accumulation on the front of the wafer to avoid the dielectric breakdown of your wafer or your structures. There is some possibility that some structures are already leaking charge to the electrode that the wafer is sitting on and other structures are isolated in such a way that they accumulate a charge, eventually discharging to an adjacent less charged structure and causing vaporization of materials and a thermal shock that sometimes breaks the wafer.
Hi guys,
What can be tested easily without opening the chamber and connecting an "external" element is to play directly on the plasma which is the SOURCE of the charges. The idea is to decomposate your etch process in several small duration etch steps. The important point here is that you need to switch off the source power between each steps so as to make the plasma charges (positives and negatives ones) to collapse on the wafer, helping thus the global wafer neutralisation. Nevertheless to set the right step duration is not easy but you can try several ones.
Question: what is the chemistry used in your plasma and the powers involved (source and bias ones)? furthermore what is the total duration of the etching?
Regards
Mohamed
Thanks for your response. In general the main etch takes about approx 36s but there are also other steps involved that take more time.At about 300W source RF and the chemistry is the usual standard C4F8 mix.
I am not sure about the switching off source in btw steps because for each step there is an intermediate ramp up..and the question of total time comes in play with this.
Ok, What i mean is that you may have several steps in your recipe but you should always have one MAIN etch step that will usually be longer than the others. This one, you can for instance reduce its duration by 2 or 3; which will mean that you will need to lanch your global recipe 2 or 3 times to finish your whole etch profile. Of course it will not be perfectly similar in term of global etch duration but the aim here is to see if the arcing still apperas or not.
Regards
Mohamed
Via patterning arcing in dry etch or ash process should probably be the insulating dielectrics breakdown model caused by RF plasma effects, ie plasma induced damage. For process point of approach, RF plasma etching course could be optimized, such as one shot long duration plasma etching separated into several short duration steps, RF plasma power lowered particularly at the end of etching, etc.
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