This ULP BGR is designed for a current of 10nA in each branch and the value of resistor is 2.9M ohm. I try to break the loop to find the phase margin using stb analysis, but where ever i broke the loop using iprobe, it returns with a message of loop gain
The current is normally mirrored back from M7&M8 to M6&M4 in conventional implementations. Simulation: you can start by checking minimum VDD from which the current stabilizes, check also reference voltage/current against temperature variation, etc.
Quote: I try to break the loop to find the phase margin using stb analysis, but where ever i broke the loop using iprobe ....
Why did you use an iprobe? Please note that the test source must be inserted into the loop without disturbing (1) the normalDC operational point and (2) the loading characteristics at the breaking.
Do you know and apply the fundamental work of Middlebrook concerning loop gain simulation?
I have a question regarding STB in cadence should I set the operating point with STB analysis or not important? also, another question when I get the loop gain I found it below 0 dB what does it mean does that mean that there is no oscillation and the system is stable?
verify the operating point of the circuit through DC simulation, make sure the circuit is operating at desired voltages. To do STB analysis get help from youtube tutorials.
Loop gain less than zero meaning that system is unstable. Loop gain = AOL.B
AOL = open loop gain, B = feed back factor, ACL = closed loop gain.
ACL = AOL/(1+ AOL.B) as loop gain = -ve, ACL goes to infinity.so unstable system.
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