Respected readers, I am working with a totem pole PFC circuit. In an experimental study, I face a problem of high-frequency notches in source voltage (Yellow one). I found an explanation behind this. It happens because of source inductance, which gives an L(di/dt) effect at the switching frequency. Is this problem inevitable or is there a solution for it? Please give me a suggestion for it. I will be thankful to you.
On the web, you can read very good papers with calculations and printed circuits. That may help you to find your errors . Your phase margin may be too small in one loop ...Some peaple use a notch filter.
https://www.infineon.com/dgdl/Infineon-Design_guide_Gallium_Nitride-CoolGaN_totem-pole_PFC_power_loss_modeling-ApplicationNotes-v01_00-EN.pdf?fileId=5546d4626d82c047016d95daec4a769a
https://gansystems.com/wp-content/uploads/2018/01/GS665BTP-REF-rev170905.pdf
https://www.transphormusa.com/sites/default/files/transphorm/news/Totem-pole%20paper_0.pdf
Saprativ Saha, Have you placed an EMI filter at the input of the totem pole PFC rectifier?
Saprativ Saha, Because of high frequency switching (switching voltages and currents), signals with high frequencies appear at the grid voltage. Also, common mode voltage (CMV) is the root cause of this problem. Consequently, it is preferable to use a low-pass (EMI) filter at the input side of PFC rectifiers.
Saprativ Saha I would like to add a few points
to the best of my knowledge, these notches in input current are a common issue (dead angle) in buck PFC converters. Totem-pole shouldn't have this issue.
1. Higher switching frequencies can help reduce notches amplitude and duration.
2. EMI filter at the input, as said by Rahul Patil
3. RC (resistor-capacitor) snubbers or RCD (resistor-capacitor-diode) snubbers can be used across the switches.
4. Minimize parasitic inductances and capacitances in the layout and component placement. Shorter and wider PCB traces can reduce parasitic inductance.
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