Is there e.g. a photo-electrochemical etching method which can be applied to (111) oriented Si wafers? Would prefer not having to buy a RIE machine and doing lithography. Is there a liquid phase etchant which is fast along and slow(er) along and (which is the opposite of what KOH is doing)? Can it be made optically assisted or enhanced so that the area being etched could be defined by a laser spot?
https://www.researchgate.net/file.PostFileLoader.html?id=53079ebccf57d7e00c8b4583&key=e0b4953079ebcbf008ere it is a schematic from CMI lab ( EPFL)
Ali, thanks for the pointer. Interesting and somehow weird at the same time. In our case, we'd still have the gold/Fe/debris mixture from the etched part. I'm not interested in pillars but in creating a single crystalline Si(111) membrane. But I like the paper. Thanks again.
Mohamed, thanks for providing it since indeed the link didn't work. I'll give it a look in a minute.
Edit: yes, that looks not bad. However, I'd prefer to
a) stay with a frame of original thickness (300-500µm) for the sake of mechanical robustness
b) have a thinned area of nearly uniform thickness, to provide uniform background in transmission x-ray imaging.
Hi,
maybe you can find some hints from the works of Fred Stevie at North Carolina State University. He has worked on this issue to prepare samples for secondary ion mass spectrometry analysis from the back of the wafers (backside-SIMS), assessing some rapid thinning methodology to ensure a good analysis throughput. He gave a nice talk/ tutorial at the last SIMS conference, perhaps you can contact him.
One of his works:
Secondary ion mass spectrometry backside analysis of barrier layers for copper diffusion
C. Gu, A. Pivovarov, R. Garcia, F. Stevie, D. Griffis, J. Moran, L. Kulig and J. F. Richards
J. Vac. Sci. Technol. B 22, 350 (2004); http://dx.doi.org/10.1116/1.1617278
What i would do, and im not certain that it works as good as i imagine is trying a wet etch process. Mask the wafer with SiN or SiO2 whatever you have, create windows that are in the right size (final membrane size + wafer thickness times sinus etching angle). Then i would go for KoH etching and reduce the thickness of the membrane to roughly 50 microns. There are recipes out there, that makes KoH etch almost perfectly flat surface. Then reduce the potential of the KoH for example by cooling and then very slowly reduce the thickness.
Of course it might be very hard to have a precice thickness, and it would be a (100) membrane, but that is the best solution i came up with right ahead.
Then the idea would be to use a SOI-Wafer. That is Si-SiO-Si, the thickness of the carrierwafer is 500um and the sio and si layers vary. The upper si layer can be very thin (i found a supplier with 2um, maybe 1um is possible) and can be in any direction (111 is no problem). Just protect the thin layer, etch though the entire wafer, with the sio as an etch stop. Remove the sio and you have an 1-2um membrane with 111 oriantation, almost perfect flatness and a mechanically stable wafer.
SOI wafer can be bought, for example here:
http://www.ultrasil.com
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