Dear Mike,

I am quite sceptical about the whole thing - lowering of the Schottky barrier due to "image force" ?!! . This should not be confused with existence with potential drops across various possible ultra-thin oxides forming at the interface !

There is in fact no theoretical justification for this effect and the most sensitive experiments (Electrical Impedance Spectroscopy) that in fact can monitor band bending right at the interface through measurement of the real part of the electrical impedance as a function of dc voltage bias have never required anything like barrier height shifts/lowering.

I would greatly appreciate if you could "teach me otherwise". Any reference and direct proof would be appreciated. Otherwise just be aware of this "uncertainty" in your work.

With best regards

Petr

Dear Petr,

thank you for answering and open a discussion. What do you mean in detail with the potential drops, dipole lowering effects or other ones?

I agree, the effect never was measured due to my knowledge. It is the same dilemma as for Fermi level pinning, am I right? No experiment justified the theoretical thoughts...

Best

Mike

Dear Mike,

I am on the way to abroad, so right now very quickly and when I come back (24th January) we can continue if you think it  worthwhile:

1. if you have a thin (two monolayers and more) natural oxide on the top of your semiconductor (always there in Si for example) and metal electrode on top of this, then it is in fact MOS structure (Metal-Oxide-Semiconductor) and the will be a drop in potential across this thin oxide that can look from outside as an effective barrier lowering of the Schottky barrier. The reason is that there will be a finite charge transfer across the oxide (the cause is the difference in the chemical potential between the metal and the semiconductor) and an "elemental" dipole will form (some positive charge-oxide-some negative charge), the rest of the non-zero charge density residing in the semiconductor. That is what I meant by the potential drop and dipole lowering of the barrier.

2. I think the Fermi level pinning is slightly different and in fact, it can be inferred from EIS experiments, at least in principle. But even here, peoples often use it when they can not explain something. So you ar right.

All for now

With best regards

Petr 

Dear Petr, 

that is okay... thank you for you fast reply. Lets continue, when you are back...

Best

Mike

Hi Petr,

in the meantime I had the chance to clarify what happens in the simulations. This is more or less clear for us atm. To continue our discussion we had, I totally agree with you arguments. Both effects explain the identical phenomenon in a limited range. The question which is open, which one is dominating at a certain point. Furthermore, preparation of structures, devices or even MS interface require special care to protect against unwanted dipole effects in upcoming projects and samples. Additionally, how good are samples and results regarding the SBL effect which have been built several years ago???

Best

Mike

Dear Mike,

yes, in the device production, there are quite complicated protocols to assure "perfect" interfaces. To get rid of native oxide SiO2, something called "HF dip" is used in conjunction with various cleaning agents (like ultra pure water).

Once formed and cupped by the metal electrode, the native  oxide should not change in time, although other things can. My experience has been that for example, after some 5 years I have noticed that EIS spectra of my Schottky Au-Si-Au samples changed, but this was different effect - in-diffusion of the electrode material(Au) into Silicon (the depletion resistance changed) and formation of a Au deep level(s) in the gap of Si. So, here I think, is not a simple answer. But remember, that what we "amateurs" fabricate is not what the Chip makers fabricate. There I think 20 years performance is a rule.

With best regards

Petr

Sure, as chip foundry 20 years performance is a rule... to be in you specification is a must over lifetime in the expected ranges. But also keep in mind, to be aware of effects that might occur you need to know of them and for sure show that they exist. There of course the "amateurs" are needed to offer those.

I agree Till, that is why it is so important to show the hole chain to be sure what you present is reality...

Best

Mike

We are pleased to announce that our contribution "Simulation Framework for Barrier Lowering in Schottky Barrier MOSFETs" is accepted for presentation at MIXDES 2017 conference.

In this paper we present a simulation framework to account for the Schottky barrier lowering models in SB-MOSFETs within the Synopsys TCAD Sentaurus tool-chain. The improved Schottky barrier lowering model for field emission is considered. A strategy to extract the different current components and thus predict accurately the on- and off-current regions are adressed.