what is the issue?

In our institute, for research work, using synopsys DC. What are ur issues? Give details.

how to get delay of our design from timing report......as timing report give information about slack,required time,arrival time,and all

First of all you can't rely on timing reports of design compiler. Because the engine of design compiler is

1) to optimize the RTL in to a gate level netlist.

2) the libraries you use in design compiler are called zero wire load models, where all the nets are considered to be of zero delay. In a design, timing is dependent on nets as much as your delays of logic cells.

3) so you can not decide the timing performance of a design based on design compilers timing report. but you can decide whether you can go a head for physical implementation of the design based on this timing report provided your setup is proper and all the design constraints you have used for synthesis are proper.

to get to know the actual delays you have to see the timing of the design using primetime.

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Coming to timing report of the design be it in Design Compiler or Primetime..

No offense but, i suggest you to understand

1) what are the possible paths that your design will have like 

    i) in to out paths

    ii) in to reg paths

    iii) reg to reg paths

    iv) reg to out paths.

2) understand what is setup and what is hold timing

3) If you know all the above concepts, Now the key is which of the above mentioned path will influence the whole timing of your design.

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command to get the timing report is 

report_timing -delay_type max/min -inputs -nets -transition -capacitance -crosstalk_delta -nworst 100 -slack_lesser_than 0.000 -exclude [ ports*] -significant_digits 4

now you will get hundred paths, where your timing paths are failing with slack less than 0.

Start analyzing the paths and you will understand why you are not able to meet the timing...

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Please go through selected chapters of Static Timing Analysis for Nanometer Designs: A Practical Approach Book by Jayaram Bhasker. you will understand everything in no time.

Pardon me for not giving me the direct answer. I believe you will learn more if you start reading this book. please let me know if you are facing any problem in understanding the concepts... will be happy to help.. All the best

@Praveen Sir thanks a lot for giving such a good guidance....i studied some part of sta  Already and have some doubts in it...i will post my doubts..please answer them.And sir in this book tell the important part...or one has to cover all things?

Dont Sir me please :-) 

Please refer to chapter 1,2,4,5,6 and 8.. if you have enough time please read the whole book. Open to clear your doubts. All the best

@Praveen i have one doubt while calculating max freq of ckt...for that first we have to find Tmin....For Tmin we generally use equation Tmin=Tclk-q+Combination delay+setup time-Slack

so my doubt is why we subtract slack time for cal max freq....as next clk get stated after slack....so why we dont add it?

Hi Ritika,

Lets go to the basics before answering your question.

1) When we start any design we have certain requirements out of which frequency is the crucial factor. Inverse of Fmax i.e, the maximum frequency at which a design can operate will give you the Tmin i.e., minimum time period required for the design to operate without any timing violations. 

2) lets rearrange the your Tmin Equation

Slack=Tclk-q+Combination delay+setup time-Tmin (Ideal Condition)

3) Please look at the attached pic... 

Arrival_TimeFF2:D = d1 + d2

Required_TimeFF2:D = T + d3 - d4

SlackFF2:D = Required_TimeFF2:D - Arrival_TimeFF2:D --> This is how you get to know the slack of a timing path.

4) From the above 3 statements we can understand that Setup Slack be it -ve or +ve of a timing path is dependent on delay of the combo logic between the two flops since we can't change the clk-q delay/setup time of flops or the frequency. Since frequency is decided even before you start a design. 

5) So your understanding of the frequency or Tclk(clock period) is little deviated from the reality(due to books of course). Coming back to adding slack,  IF there is -ve slack in a timing path we try and bring it down to Zero, which means the required time for data to be stable and actual time at which the data is available is same. Meaning there is no timing violation of the path.  For +ve slack, the data is available before the require time. 

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Why we cant add slack??

Because a Flop is edge triggered. i.e., your slack is only available for that path not for the next one. If you are working on latch based design, your idea is a very good fit. because latches are level sensitive, if there is any positive slack for the current path, next path can use this slack to its advantage providing more setup margin. This is called cycle stealing or time borrowing.

Please refer this link for clear idea on cycle stealing on latch based designs.

http://www.ece.ncsu.edu/asic/2012/docs/timing.pdf

Hope this helps. Am sure you will have more questions. Keep me posted

Regards,

PRaveen.

Thank U Praveen Gudala for your detailed answer

@Praveen Gudala  thankyou for such a nice explanation.

i have one doubt in finding required time.As we are finding required time for same clk cycle why you add (T) time period and from how this equation T+d3-d4 comes?

@Sivanandam sir.. My pleasure

@Ritika... Answer to your question is in the image I attached. Find it out and let me know your understanding.. :-) quiz time

• Which time represent computation time in design compiler timing report? iS it a data arrival time? or anything else

can you be specific? which computation time?

@Praveen Gudala when we have to compare two design by critical path slack parameter...then design having greater critical slack path is better or not? for delay analysis

Greater critical path design is better, when we go for back end analysis due to more slack. But greater critical path slack not necessary, because it that time design may ideal. So better increase frequency and reduce slack time. It will increase system speed. 

I want to synthesize a benchmark circuit using Synopsys Design Compiler but I don't know how to do or where to start?plz help me with procedure?

I am studying on it. How can I work with you?