Sorry, this is confusing. First, flip-flops cannot be initialised. This is often used in code targeting FPGAs, but in ASICs this is not allowed. The correct terminology/usage is that a flop can be reset to any value that you want.

Compiler doesn't care about order of events, it cares whether there is a reset or there isn't. If it sees a reset in the logic description, it will instantiate a resetable flip-flop for you.

As to synthesis results, don't make hushed conclusions just by looking at the netlist. The compiler has the freedom to change your design to make it more efficient. A flop that you expected to be initialized to zero might be initialized to 1, and then be followed by an inverter. What you should be looking at is the simulation of the synthesized netlist. I guarantee you it will match the original design intent.

Thanks a lot Samuel Pagliarini for the detailed explanation. Actually, I am was analysing the Design Optimization with DC compiler, and I didn't point that out completely in my initial query.

My test design had one FF. The output of the FF (o_out) was connected back to its d_in through an XOR operation with i_data. i.e.,

d_in There is a feedback loop from output of FF back to its input pin

I instantiated two such design. Both designs are given the same set of inputs.

Only one output is selected based on the 'sel' signal.

My expectation is- Since both instances are of the same design and are given the same set of inputs, the compiler should optimize the design and reduce to only 1 FF (instead of 2)

Observation-> Compiler doesn't optimize this design. But if I remove the feedback loop from the design, it does the optimization. So, I was thinking in the direction that since it has a feedback loop, and current states of the 2 different FFs can be different, therefore the DC compiler is not optimizing. Inorder to confirm this theory I was hoping for a way to tell DC compiler that initially my design would be under reset (thus the two different FFs would be in the same initial state), and thus the compiler should do this obvious optimization.

I have attached schematic after synthesis.

1. Test Design

2. Two instances of test design with a Mux.

Regards

Chirag

I think you have stumbled upon a tool optimization feature.

In my synthesizer (cadence genus), I get two flops if I run it with low effort. In high effort, the logic becomes a single flop.

See my code (attached).

Thanks Samuel Pagliarini, for checking with cadence.

I tried to use the high effort setting, but that didn't help. I am currently using the following compilation command with Synopsys DC

compile_ultra -map_effort high

Are you using something similar with Cadence too? I believe there should be some setting which makes this optimization even with Synopsys.

I checked with my verilog file, as well as yours (They differs in terms of a MUX). But none of them optimizes.

My code is attached.

I don't think SDC has anything to do with such optimization.

It is interesting though, as I remember seeing DC merging counters with identical enable signals, which is exactly your case (1-bit counters)

Hi Tzachi Noy .

Yes, its is quite strange. Samuel Pagliarini mentioned that it does optimize with Cadence Genus, but I still didn't find why is it not optimizing with DC for me.

I even checked Synopsys SolvNet for information on that but couldn't find anything useful to me yet.

Do you remember, if you used any specific settings for the compiler for optimizing such circuits? I'm still looking for solution to this problem.