As far as I understand Nidhin, for eg: Xilinx's CLB /IOB/path delay of an interconnect between successive CLBs are all characterized /uniform/equal . The designs are built on characterizing each block (cell) and optimized , so that if you have n # of CLBs in cascade then they are sum (depending on how mapping of blocks are done )

I would recommend you looking at a particular products timing specs .

There are people using FPGAs as high precision TDCs (time-to-digital converters). Since the delay of every element is not the same they have to calibrate for this. You should have a look at how they do this.

you can estimate some delay using the post place & route simulation and/or the time report