T S Nidhin | Indira Gandhi Centre for Atomic Research

T S Nidhin

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Questions related from T S Nidhin

How to avoid signal optimization during synthesis in Xilinx FPGAs?

while constructing a delay circuit

06 June 2017 3,199 0 View

How to overcome setup time and hold time violations?

ie., metastability

05 May 2017 894 4 View

How to measure the path delay of internal element (for example : Flip-flop) to internal element of the design implemented in SRAM FPGA (Xilinx)?

also between input buffer to output buffer?

01 January 1970 2,634 3 View