If the data signal comes from an external source, the usual way is to have two flipflops resp. registers in series, both triggered by the same clock signal. Of course, this delays the data signal by one clock cycle.
If the data signal is an internal one, normally the problem can be solved by careful design.
If it is a control signal, indeed two flip-flops are the usual solution. However, if it is a high speed bus transfer with a different clock, then a FIFO may be required. Between these two extremes, there are other cases such as the two clocks having the same frequency but varying phases (usually due to skew). A helpful tutorial can be found at:
http://webee.technion.ac.il/~ran/papers/Metastability%20and%20Synchronizers.posted.pdf
VK: Proper flip-flop operation is guaranteed when the ‘new data’ at the output of the sending flip-flop arrives at the input of the receiving flip-flop after the hold time of that receiving flip-flop.
As I read it, that seems to be the wrong way round. The new data needs to reach the second FF before the next clock edge by at least the setup time. It then needs to be stable until at least the hold time after the clock edge.
Metastability however is concerned with transients related (usually) to changes on an asynchronous input signal being latched into the first FF within a synchronous design.
While the hold time violation can be solved by inserting delay between the launching and capturing FF, nevertheless, one shall be careful that this does not create a new critical path. On the other hand, setup time violations can be solved by increasing the clock period. However, this may not be always acceptable. Within the boundary of fixed clock period, one possible approach to solve setup time violation is to reduce the logic delay between the FFs. Clock skew between launching and capturing flip flops also have their positive/negative implications one setup and hold time violations. One shall actually take all these things into account while finding a possible solution for riming violations!
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