PDK files are basic need for any circuit design of Cadence virtuoso. When new technology comes then for device/circuit design, the pdk files should be present in library. Many times problem arises due to missing pdk files.
Let's say we have a standard, regular hexagonal honeycomb with a 3-arm primitive unit cell (something like the figure attached; the figure is only representative and not drawn to scale). The...
07 August 2024 1,937 1 View
While working on caisson foundation, I applied static vertical load
25 July 2024 9,357 1 View
We have seen in the literature that Ang-1 can be considered as one of the markers. We need information about few more markers.
01 June 2024 9,650 1 View
Notch 3 can be considered as marker for stable blood vessel formation?
01 June 2024 9,788 0 View
Both angiogenesis and arteriogenesis are needed to make stable blood vessel formation. Ang-1 is one of the markers for stable blood vessel formation. Can you please suggest names of few more...
01 June 2024 1,912 1 View
Globally what are the Research opportunities in stabilizing overburden dump slopes in opencast mining?
16 May 2024 5,334 1 View
Temperature and sudden rain, I am observing this year in my areas.
13 May 2024 6,223 2 View
Conceptual Designing of aircraft provides a major role in designing of aircraft. Let's consider the weight estimation in it. For electric aircrafts its fuel variation is " zero ". Hence W|f is...
18 March 2024 946 3 View
I conducted X-ray diffraction (XRD) investigation on my chitosan sample and need assistance interpreting its diffractogram. If possible, could someone share the chitosan JCPDS card number with me?...
01 March 2024 2,080 4 View
PTFE: Polytetrefluoroethylene or teflon and PPL: Polypropiolactone
14 February 2024 6,223 0 View
I want to simulate an ISFET Array with a read-out circuit in Cadence Virtuoso which can detect electrolyte from a sample solution.
12 June 2024 6,441 0 View
i make a design topology of mixer For my graduation project working at 28 Ghz on cadence with UMC pdk and get this result S(2,1) 3.5db but when trying to make same topology with another pdk on...
09 June 2024 9,729 3 View
I want to know how to attach the Gate all around FET library can be 3nm to cadence tool. Where we can get the 3nm GAAFET Library.
17 April 2024 2,627 0 View
I have managed to Cadence generic PDK 45nm from the web [1] and found it very good. If somebody could send or link the Generic cadence FinFet PDK "cds_ff_mpt" for studying that'd be great. [1] I...
29 February 2024 5,561 1 View
I want to extract the electrical properties of MOSCAP in cadence virtuoso but I don't know the exact method how to measure resistance and capacitance and other properties of MOSCAP
05 December 2023 4,667 0 View
NW.E.3 : Minimum Nwell enclosure of Stradled NBL>=0.24um
05 November 2023 8,538 0 View
The comparison is made at varying data 8 times, 4 times, 2 times, 1 time and 0 time for 8 active high clock pulses for switching activity factor of 100%, 50%, 25%, 12.5% and 0%.
12 October 2023 4,694 2 View
My Question is when the VG is directly applied to gate of mosfet, in CS amp, though vds> vgs-vth is satisfied, the fet is not in saturation region because vgd> vgs-vth. How to decrease the vgd to...
20 August 2023 3,306 0 View
I want to draw a circuit for a thermistor.
18 August 2023 6,161 0 View
I am troubling to find that in cadence how read current of single bit cell (6T SRAM ) is measured ? i am doing DC simulation for this but how to make Q / Qbr = 0. Does any one help...
31 July 2023 1,641 1 View