Dear Sir, I would like to suggest you something which may beneficial in terms of implementation of your CNTFET in Cadence platform.

First of all if the compact model for the device is available then it can be implemented easily in Cadence platform.

If not then you can go for exporting all the I-V and C-V parameters for the entire rage of voltages for example -1 V to 1V with a step size of 0.01. Devlope Verilog A based code using the exported data and take it to Cadence platform. For more detail you can see my published article in IEEE transactions on electron devices, vol 67, no 3, pp 1285- 1292.

Hi

Please check the following link. I believe it will help you.

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/31170/creating-a-cntfet-model-in-cadence-using-veriloga

Regards

Dear Manas,

You can consider that both devices as FET transistors and that the MOSFET model can be applied on the two devices. In the sense that that you can use the dot model parameters of the MOSFET for both devices. In this way you need to extract model parameters of the CNTFET.

For more information please follow the paper in the link: Article Device and circuit-level performance of carbon nanotube fiel...

Best wishes

Thank you for your valuable comments.............

is connecting couple node of pcnfet to vdd is correct sir. someone please help me