Dear all,
I have designed my circuit in VHDL in Xilinx tool.Can any one help in Area and Delay analysis of the design please.How to do?what is the procedure?
First of all you have to run "Synthesis" and "Implementation". After that, you will see what resources your design needs to be implemented in "Design Summary".
You have to look at the Post-PAR (Place and Route) Report, this is where ISE explains whether the timing constraints of your design are met, what the critical path of your design is and up to what clock frequency your design can run! It will also let you know of how many slices, FF, IOBs have been used etc.
Keep in mind that the numbers you get after Synthesis are only ISE's estimations - only PAR (part of "Implementation") results in accurate numbers!
Words given by Mr. Nikolaos Kyparissas is Absolutely Correct. Go ahead Mr. Kumar Panda.
Even though after PAR is executed, you don't have an estimation of how big is your design, in terms of area. You may know the number of flip-flops, DSP blocks and BRAMs, but you have no idea how big your design is. All the resources may be spread out in the entire device, w/o optimizing the area. What you can do, is based on synthesis results, try to define the area for all your resources, including the position (in terms of X and Y), using the AREA_GROUP constrain, and let PAR know about this, so PAR will make the best effort to fit your design. Even though is not complete, you may take a look at the following paper (Partial Region and Bitstream Cost Models for Hardware Multitasking on Partially Reconfigurable FPGAs), so you may optimize the size of your design:
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7284295&filter%3DAND%28p_IS_Number%3A7284273%29
Regards,
Aurelio Morales-Villanueva is totally correct, you might want to consider using Planahead too after PAR to customize your design's placement if needed!
In vertex -7 if
Circuit A consume 1800 LUT and 70 FF
Circuit B consume 650 LUT and 400 FF
which one is better.
I mean how LUT and FF s used by a circuit is compared with another circuit.
Dear Gyanendra Singh , I think we cannot compare Circuit A against Circuit B (assuming they perform the same function), unless we specify the same area for both circuits. Assuming no DSP or BRAM, I think we can look at how many CLBs are used in the area. With a small area, chances are that you may have routing problems. Regards,
Dear Sir, thanks for your sincere reply. If we want to compare both circuit area wise then which one is better. Kindly suggest me in his regard.
Dear Gyanendra Singh , since there is no much info, I have to assume that LUTs are not connected to FFs. Taking into account that for 7-Series devices, each CLB has 8 LUTs and 16 FFs (check UG474 document from Xilinx), I would say that Circuit A is bigger. You may check the paper "Partial Region and Bitstream Cost Models for Hardware Multitasking on Partially Reconfigurable FPGAs" to give you an idea about the subject. Regards,
Thank you all.
In vivado tool, if we want to note how much area is consumed by a design,then what is the TCL command?
Is it report_utilization ???
Or any other method is there??
Because report_area command not working.
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