The performance degrades with increasing clock speed, so DAC speed is defined in conjunction with parameters such as SNDR, SFDR, etc. You can run SFDR simulation.

Dear Nupur,

You may input a test sequence forming a complete stair case of all possible values at the output of the converter. Then you increase the co lock speed till an amount of acceptable distortion is not exceeded. May be the linearity is taken as a performance parameter. may be also the spurious free dynamic range.

In this case you may input a test vector in form of sine wave and measure harmonic distortion and the spurious free DR by analyzing the output distorted waveform. Then you increase the frequency of the sine till the upper bound of the allowed distortion or the DR arrived. Then this frequency will be considered the frequency limit.

Best wishes