Hi,

please check the following thread:

http://www.edaboard.com/thread69923.html

Why do you want to convert Verilog netlist into SPICE netlist?

Are you going to simulate the synthesized desing? Electrical simulation of  gate level design is possible only if you have got transistor level representation of gates  (so call standard cells) including parasitic RC elements. Such approach is impractical and usually impossible since transistor level representations of gates are not distributed.  

If you want to simulate your gate level design you have use that same test bench you simulated the VHDL model and replace the VHDL model of  your design with the synthesis result. All HDL simulators (from Cadence or Synopsys) can simulate such a mixed (VHDL-Verilog) project. You have to  also include in your project the Verilog description of the target library. This library IS always distributed by the  technology provider.

There is one more thing. To obtain proper  timing estimation you have to generate during synthesis SDF file which includes description of delays of  every gate in the design. This is VERY important. Each instance of a gate have slightly different delay due to different load. Only in this way you can detect glitches.

The SDF file should provided during simulation of the gate level design (this call back annotation).

Please see following link:

http://www.silvaco.com/products/digital_cad/spice_netlist_verilog_gates_conversion/catalyst_ad.html