You can contact coreEl , Bangaluru,India

I would like to know whether you define constraint in your design? Do you used any Xilinx reference design in your implementation? 

i have my own program using xillinix ISE to check this design i want to know how i made the UCF file for z board zynq 7000 the out put and input constrain

 how can i found coreEl , Bangaluru,India

Xilinx ISE create UCF file .If you click top module in process menu you should select user constraint , in user constraint run I/O pin planning , in I/O pin planing you can assign signal's to the pins (It has pins name) and after that ISE make UCF file. 

By clicking on the top module in Xillinx ISE you will find I/O pin planning in User Constrain, which you have to click on. These will open a new window (new simulator) called PlanAhead. In which there is a option of I/O ports where you can define the pin number. These will generate your .ucf file like attached here with.     

Even you can directly modify the same file by just changing the port name and pin number.No need to open PlanAhead for further corrections.