Actually, the aspect ratio of the lithographic patterns should be defined as height/width (Hfin/Wfin). However, some literatures have been reported as Wfin/Hfin. Both of them are fine. The classification of 3D-MOSFET device is not only depends on the Hfin/Wfin but also related to the fabrication process.

For planar device, no fin structure under the gate pattern (Hfin = 0, Wfin = 0).

In case of double-gate FinFET, it can be classified by the available of "hard mask" on the top surface of fin structure. This hard mask prevent the electric field to induce the inversion channel on the top surface. Then only the two sidewall surface on Fin structure acts like a gate.

In case of Trigate, no "hard mask" deposited on the top surface. Then three gates (top + 2 sidewall) are working together.

Moreover, if Wfin >> Hfin, the top surface orientation play an dominant for device characteristics and acts like a planar device with micro-roughness on the Si surface (if p-Si(100) sub is used Wfin (in micron) and Hfin (in nm), top fin is (100) and sidewall is (110). However, if Wfin

Thank you Nithi, for your valuable clarification of my doubts. 

Although both definitions are accepted, as Nithi has mentioned, the more correct definition of FinFET  aspect ratio is Hfin/Wfin. This makes sense, because one of challenging issues now in FinFET is realizing the so-called ultra-high aspect ratio ( larger height , smaller width) devices... However, some groups define aspect ratio as  Wfin/Hfin which is also acceptable and likely due to the adoption of the width-to-height aspect ratio definition in monitors and televisions. Nevertheless, to be safe, it is always prudent to explicitly state the definition as in "height-to-width aspect ratio" in writing papers