you can see in report itself

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/ug786_PowerMethodology.pdf

By Using Xpower

Power will be visible in synthesis report. If you want draw graph then go for Xpower tool and vary the current and voltage according to the requirements

Hello Shoba,

Are you constrained to using ISE because of a specific device you are using or can you move to one of the newer versions of Vivado?

If you move to Vivado, the power estimation in Vivado is much better and you have the option of estimating post synthesis as well as post route power estimation.The way to do this would be to run a post synthesis or a post route timing simulation. In the simulation options you need to enable "saif" file option, which logs the signal activity information. The related options would also need to be filled in correctly. Once the simulations are complete, Vivado has an option "Report Power" under Implementation. In the "Report simulation" dialog box you can provide the "saif" file you generated in simulation and you will get a very accurate estimate of the power.

This of course is dependent on how robust and exhaustive your testbench is, when you performed the simulations. If the test bench is not exhaustive, and is a not a true representation of the typical inputs that your design will encounter, then the power estimation may will also be incorrect.

I hope my answer helps you get started. In case you have any further questions, please feel free to post them here and I will try and answer them the best I can.

What is the saif file option

Anil,

If you select the simulation settings in Vivado, you are presented with the following dialog box, where you can select options to log all signal activity in a saif file. A saif file can be considered as a reduced and abstracted version of the vcd file.

- Prashant

Go to Tools Menu and You will see XPower Analyzer in Tools Menu in Xilinx ISE.  

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I have had my issues with power estimation using ISE. But over years I have come up with certain steps that help in estimating power dissipation with a high confidence level. Note that power dissipation is a strong function of the switching activity (number of 0 to 1 transitions) in a circuit. So apart from providing a power constraint file (using constraint editor) you will also have to provide some realistic switching activity using a  VCD (value change dump file). The following tips may be helpful. 

01) Try to implement your multiplier in a synchronous environment i.e. either pipeline your multiplier design, or at least ensure that you are providing registered inputs and getting registered outputs. In any case a global clock signal should be a part of your design. The reason for such an approach is that, inherently FPGAs are synchronous devices and it is better to adhere to synchronous practices while using them as implementation platforms. The inclusion of a clock signal provides this synchronous description.

02) Now that the clock has been included in the design, place a constraint on the clock (like period, duty cycle). Additionally define constraint for input and output offsets that define the timing relations between the clock and the input and output signals.

03) Select your target device. If your are intending to dump the design on the FPGA device then ensure that the nets are locked on appropriate pin locations of the devices. Again this description has to be provided in the constraint file itself.

04) Now for the switching activity. Here is what I do:

i) First design a test bench.

ii) Go for post route simulation. It will take some time.

iii) Once the simulation window pops up initiate a vcd file using the command:

vcd dumpfile power1.vcd

then use this command

vcd dumpvars -m/uut

Now start giving inputs to check the functionality of the design. Each set of inputs will correspond to some switching activity in the multiplier that will be stored in the power1.vcd file. The more inputs you give, more accurate will be the power results. So try to give at least 20 to 25 input sequences.

Finally use this command

vcd dumpflush

close the simulator window.

iv) Now go back to ISE design environment. Initiate the Xpower analyzer tool under place and route. This will pop up the Xpower analyzer environment.

v) go to file menu and add the .ncd file of your design. Also include the power constraint file (that is automatically developed from ucf file). Also include the vcd (power1.vcd) file.

vi) Xpower will now generate the power data based on the provided inputs. Check out what is the confidence level using one of the tabs on the left side menu. You may also generate the advanced power report from the tools menu that will give you complete details.

I have had some experience with multiplier designs. If you need any other help, feel free to ask.

Good Luck!

Best use xpower tool.

I used it. It is working