ame across an error in PEX.
In LPE .tec file, path to lvs rule file is given with Include directive.In LVS Rule file #DEFINE PEXRUN is uncommented for pexrun. Error encountered on compiling .tec file
ERROR PEX5 in line 2762 in .tec file.
capacitance or resistance extraction layer not properly configured in CONNECT operation:ME9_C
I amnunable to figure out the issue with this rulefile.Would like to know if such an error is encountered in UMC65nm
Here is a summary of the possible solutions:
- Check the LPE .tec file to make sure that the layer is defined correctly and that the path to the layer is correct.
- Verify that the layer is present in the design database.
- If the layer is present in the design database, check the layer configuration to make sure that it is configured properly for capacitance or resistance extraction.
- Check the LAYER MAP, PEX MAP, and PEX ALIAS statements to see if ME9_C is part of a group with another name that is in a CONNECT statement, or if ME9_C actually connects to any of the other layers after it.
- Restart the Calibre PEX tool and the design database.
- Try using a different LPE .tec file.
- If you are using a UMC65nm design, contact Calibre support to report the issue.
If you have already tried all of these solutions and you are still unable to resolve the issue, you may need to contact your foundry for assistance.
Additional tips:
- Make sure that you are using the latest version of the Calibre PEX tool and the UMC65nm PDK.
- Check the Calibre documentation for more information on how to configure capacitance and resistance extraction.
- If you are using a custom LPE .tec file, make sure that it is compatible with the Calibre PEX tool and the UMC65nm PDK.
https://www.edaboard.com/threads/cailbre-pex-error-with-umc65nm.346049/
https://www.edaboard.com/threads/calibre-pex-error-umc65nm.408419/
https://community.sw.siemens.com/s/question/0D54O00006eo5f1SAA/tsmc-65nm-pdk-crn65-with-calibre-lvsdrcpex
I hope this information is helpful.
Good luck
Thank you.I contacted foundry. In LVS file I had to define the correct metal-stack, identical to the XRC tec-file.Ther were multiple stacks in LVS.By default one was active.I commented it and activated the one appropriately corresponding to the metal stack used in LPE .tec file,issue got resolved.
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