Hi every body
i want to simulate a simple transistor in Silvaco to see the I-Vg in the simulator. unfortunately i could not get the good result .i check my structure more time. but i could not find the problem. you could find code and also the result of the simulation in attached files. I will be highly grateful if anyone could help me to know the problam
Regards
Dear Mr. Saradhi,
As you see in the result the drain current is negative but when i simulate it versus drain current versus drain voltage as you can find in attached file it is positive. also as i read in the paper, the threshold voltage of the structure have to be around -1.2 . these are my problems in my results
Hello Dear Amine,
I checked it many times. But i could not find any problem. Can you please tell me about your suggestion more. can you please write your mine in code. because i could not got it.
Thank you for your time and regards
Hello dear
Change the meshing dnt use fine meshing every where. ..
And without applyng a gate voltage u cant get ur id vd curve.. so check ur solve command in ur programme...
Use this command
Solve init
Save outfile=solve1
Load infile=solve1
Log outfile=test.log
Solve vgate=0.6
Solve vdrain=0.0 vstep=0.1 vfinal=1.5 name=drain..
Same as it is
If u want to simulate id vg then change the bias and chnge the biasingname
Hope u will get ur result
Good luck...
check meshing in channel region, doping value in channel , why using uniform doping throughout the channel change it for better result
Thank you for your reply. but how i can change it for better meshing? I will be highly appreciate if you give me more information. because i am new in silvaco
thank you and regards
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