Ajay Rupani

16 Questions 5 Answers 0 Followers

Questions related from Ajay Rupani

How to implement the GDI technique in MVL-based digital logic circuits?

I need to implement the GDI technique in MVL-based digital logic circuits.

12 March 2024 1,331 0 View

How to perform DC analysis to calculate Noise Margin of NAND and NOR gates using HSPICE ?

DC analysis to calculate the Noise Margin of NAND and NOR gates using HSPICE.

16 October 2023 876 0 View

How to draw the layout of the CNTFET-based standard quaternary inverter using Synopsys HSPICE ?

How to draw the layout of the CNTFET-based standard quaternary inverter using Synopsys HSPICE?

12 September 2023 1,208 0 View

How to reduce the Power in Multi-valued logic circuits ?

I need to reduce power in CNTFET-based quaternary logic circuits.

24 August 2023 5,574 0 View

How to design a Voltage divider circuits using nano transistors ?

We need to design a Voltage-Divider Circuit using transistors.

04 August 2023 1,515 2 View

How to insert Noise in a Piece Wise Linear(PWL) input of a Digital Circuit using G-element of HSPICE ?

Piecewise Linear (PWL) Gxxx n+ n- VCR PWL(1) in+ in- + x1,y1 x2,y2 ... x100,y100 +

15 May 2023 2,496 0 View

How to generate a Source of Noise in a digital circuit using Synopsis Hspice ?

Generation of noise is an essential part to ensure the noise tolerance in the circuits.

24 April 2023 9,427 1 View

How to insert Noise and superimpose that noise onto input signal of a CNTFET based Quaternary logic circuit using HSPICE?

CNTFET-based quaternary logic circuits are susceptible to noise due to various sources, such as thermal noise, shot noise, and flicker noise.

28 March 2023 341 0 View

How to merge two graphs in Hspice Custom Wave Viewer ?

To calculate Static Noise Margin (SNM) from Butterfly curves.

23 March 2023 6,205 1 View

How to plot Butterfly curves for NOISE MARGIN Analysis in CNTFET based Quaternary Logic Circuits using Synopsis Hspice ?

Static noise margin analysis using butterfly curves has traditionally played a leading role in the sizing and optimization of SRAM cell structures.

16 March 2023 3,086 3 View

What should be the range of Noise Margin in Multi-valued Circuits (Ternary and Quaternary Logic Circuits) ?

Ternary logic ( R =3 ) has three logical states {0, 1, 2} Quaternary logic ( R = 4) has four logical states {0, 1, 2, 3}

16 February 2023 1,290 2 View

Any Text/Reference Book available for study on Carbon Nanotube field Effect Transistor (CNTFET) ?

Any Reference available on CNTFET: 1. CNTFET as PTL (Pass Transistor Logic) 2. CNTFET as Transmission Gate 3. Effect of Temperature on CNTFET based Circuits (Formulae showing relation between...

07 February 2023 4,128 1 View

How to calculate Noise Margin in CNTFET based quaternary logic circuits using HSPICE ?

I have designed a standard quaternary inverter using CNTFET, but need to calculate its noise margin.

20 May 2022 4,460 0 View

Which technique is best for designing Quaternary Logic Circuits using CNTFETs on Hspice 32nm Technology ?

1.Multiplexer-based 2.Innovative and Combined techniques 3.Gate-based 4. Radix Converter based 5. Others

13 April 2022 8,204 3 View

Which logic technique is better between Quaternary logic and Ternary logic for designing CNTFET based circuits ? and Why ?

At beginning era of digital design, the binary logic is used in all industrial applications. The binary logic uses 2 states i.e. 0’s and 1’s to represent each state. Since the binary logic uses 2...

27 January 2022 638 3 View

I need help to insert noise in a digital circuit in HSpice.

Which commands to use for noise insertion in digital circuits using Hspice?

01 January 1970 653 1 View