Most probably, the gate insulation is not good. Or, seeing the very low Id, your material has low carieer mobility so that only the noises are detected.

Check the fabrication process, specially deposition of insulating layer thickness and metal-organic interfaces. May be your device were severely exposed with air during fabrication process.

Thanks for useful comments. In addition i am using Ta2O5 as gate insulator through contact hole fabrication and petacene as semiconductor and Cr/Au as electrodes. i am using back exposure and liftoff techniques to fabricate the channel .

Same as Jing and Salim, Check your contacts, they are not proper. Because the current you are getting is just open circuit fluctuations. Work out with the contacts and measurement technique.

i use same semiconductor parameter analyzer (HP 4155B) for all the devices its work fine with top contact OTFTs i feel problem only in that transistor(Bottom contact) i fabricated the transistor many times but same results no change.

What do you use for connections: probes? Generally, probes can not penetrate through the semiconductor layer deposited over the contacts and in that way you do not get contacts. If this is true in your case, try to manage some part of drain and source not to be deposited by semiconductor. Because you only need semiconductor inside the channel so you can use some mask to get some clean part of source and drain to get proper contact.

@Arunandan Kumar. yes i use Probes . i am preparing short channel length transistors its not possible to use mask for semiconductor. Do u have any other idea or suggestion to make proper contact ?

can you provide me some details about source drain contacts. It would be more helpful if you can show me a picture of source and drain deposited on the substrates. What are the dimension of source and drain contacts? You are evaporating pentacene so using a shadow mask to evaporate pentacene will be good. I am sending you an attachment, according to that you can think and from the corners you can take the source drain contact.

Hi Alam,

I think Takuji Ogawas answer seems to be the most appropriate one.

What is a short channel for you? Do you mean that we can not use the gradual channel approximation?

What is the channel length you are using and what is the thickness of the gate dielectric? Also, the thickness of the dielectric.

Dilek

@Dilek Isik

I mean short channel length ..from 1um to 50um. the dielectric thickness is 180 nm(Ta2O5) and Gate is Tantalum 100nm.. semiconductor is pentacene 100nm.

@Arunandan Kumar

I am using Photomask for Gate, Contact hole and source drain electrode. On one slide there are many transistors so i cant make the gate contact open.The image of my fabricated transistor is attached

@Takuji Ogawa and Dilek Isik . I also think the insulator may be the problem. How can i improve the insulator layer what are the possible causes in the insulator layer which effect the device performance...?

Dear Mir

You asked the researchgate researchers to help you trouble shooting your organic MISFET transistors. Such questions excite me and i find my self attracted to share with the colleagues to find a correct answer. Such questions are channlings especially if the there are missing data to solve the problem which is your case. I am sorry for this long introduction.Now let us go to the matter:

The portion of the i-v points listed in the table are not conclusive except that the currents are only noise currents. The gate current is not equal the the drain current as you said in your question. I see no transistor effect.

So, your structure is not yet functioning as a transistor.

In order to get functioning devices you must be sure that each fabrication step is successful. Therefore you must at the same time of the fabrication of the circuit you have to see for the so-called and produce at the same time a test structure.

In your experiment the test structure is separate transistors. So you have to check after every fabrication step that you got the required layer with the required geometry. You have to test that optically by a microscope and electrically by a probe station.

In order to get the transistor effect the MIS structure is important and must show the conventional field effect. You have to measure and concentrate on this structure.

Additionally the source and drain metal semiconductor contacts must be rectifying of the schottky type in case of metallic semiconductor substrates.. In case of organic FET the metal organic contacts may be non recrifying or even ohmic. For more details please refer to the very useful thesis in the link:

http://www-brs.ub.ruhr-uni-bochum.de/netahtml/HSS/Diss/KaeferDaniel/diss.pdf

To be successful technological engineer you have to provide for every fabrication step checking it both optically and electrically.

If you do not follow strictly this procedure you may take much longer time to reach your target.This is my experience with the work in technology.

I hope it helps you.

Wish you success.

@ Meer, If I understood you correctly then, you are using the same dielectric for top drain and source contact transistor and bottom drain and source contact one and it is working for top drain and source one and not working for bottom source and drain one. One more thing to ask, what is the area of your source and drain contacts. I think it must be greater than 3 mm x 3 mm. If it is so then why is it so difficult for you to create a mask to evaporate pentacene. You can use an aluminum foil with an opening of 2 mmx4 mm and just stick it with your substrate in such a way that your channel comes in the opening and evaporate pentacene. You will always get some part of drain and source without pentacene over it.

I am suggesting you this way because we used to do in our lab by this way only and it works well for us. Initially we were also getting the characteristics like this only then after some discussion in our group we came to the conclusion that our contacts are not proper. That's why we adapted this way to evaporate the semiconductor. And we also have around 30 transistors in one single chip.We have chosen aluminum foil because by that we can make the openings very easily by using some scissors or cutter.

Or the second way is to have very hard probes of probably gold, molybdenum or tungsten because then they can penetrate through the semiconductor.

Looking at the structure of the transistor there may be a leak between gate and source. What are the thicknesses of the electrodes? Do you think during the metal deposition your metal diffuses through your semiconductor making contact with the other metal electrodes? I suggest you to write down the whole microfabrication process of your transistors because it seems like there is a structural problem.

When you define a channel as short the thickness of the gate dielectric is close or less than that of channel length. In your case I am not sure if it is a good idea to use short channel definition please look into this as well.

Thanks to every one for there comments . i have attached the paper with same work . only i am using Ta2O5 as dielectric.

@Arunandan Kumar

I dont know the exact dimension but its very small there more than 9 transistor on 2.5mmX2.5mm substrate. I can see any transistors with eyes..

@Dilek Isik the electrode i am using is Cr/Au 5/50nm (Cr is 5nm and Au is 50nm)

@Abdelhalim Zekry

I will also check at every step.

@Abdelhalim, Sir, I have a little doubt over the Schottky contact you mentioned. I thought that the Schottky contacts should be Ohmic rather than rectifying for a proper channeling of carriers, please correct me.

@Mir Waqas, Can you try using just 1nm of Cr rather 5nm as adhesion layer? I don't find any problem with 1nm of Cr interlayer. The reason I am telling because only few nanometers from the insulator surface the pentacene or semiconductor act as conducting channel during the operation and in your case mainly chromium is being used as contacts rather than gold.

Regarding proper contact, I would say that try the two probes on the same pad (either drain or source) and measure the resistance to confirm if that's quite low (~1Ohm??). Repeat this few many times to ensure you always have the contacts with the gold and if not then the semiconductor is coming between and only masking might help.

Dear Anup,

Thank you for your comment. It motivated me to add more details to my previous comment.