I am planning to work on a design that will involve a large number of 16-bit or 8-bit ALUs (about half a million) connected in a mesh-grid structure.. Which FPGA will be the best choice?
I think you should start vhdl or Verilog coding for that and then simulate in Xilinx ISE. While simulation 4 input have to be provided namely , family, device, package and speed. One example input may be Spartan 3E, XE3S500E, FG320, -4 respectively. With this input if your simulation runs successfully then go for that hardware spec. After simulation you can check Design Summery which will help you to decide future flexibility.
Thank you for your answer. I am familiar with the simulation environment Xilinx ISE and VHDL Programming. However, my works now are limited only to RTL Schematics and Testbench waveforms. I have designed an 8-bit ALU and some simple circuits.
I have asked this question in order to estimate the budget of the project that I want to work on. As far as I know, the logic count varies from one FPGA chip to another. And so varies the cost. Therefore it will be helpful for me if I know which chip I should go for before starting the project work.
When you are looking for large logic capacity, then I would recommend Xilinx Virtex-7 or even Xilinx UltraScale. The very smallest chips of these families start at around thousand Euros and the biggest ones cost you several (!) tens of thousands per chip. I consider anything older than that as insufficient for your goals and I consider the UltraScale+ as too new (availability might be an issue; but didn't check that). The family overview pdfs can be found here:
The largest Virtex-7, i.e. the XC7V2000T has 305 thousand slices, i.e. 1.2 million LUTs. When you really want to implement 0.5 million ALUs, then this FPGA is too small for you (as each LUT has only 1 bit output).
The largest Virtex UltraScale, i.e. the XCVU440 has 2.5 million LUTs. For your project that would mean 5 LUTs per ALU. So it is impossible to implement an 8-bit ALU here. And this estimation did not even consider the interconnect between the ALUs that might need extra LUTs for multiplexers or whatever.
If you really want to target such a big design, then you will need a multi-FPGA platform, which comes at huge cost, significant get-it-running overhead, and terrible debugging headache. By chance we are using such a platform in one of our bigger projects, but we have several people responsible for it and trying to maintain/integrate everything. If I remember correctly, then we paid 60 thousand Euros (plus tax) for it and that price contained significant University savings after long negotiations with multiple companies. The performance of multi-FPGA platforms is really slower than on a single-FPGA board, as communication between the FPGAs has to go via PCB traces. Keeping the FPGAs synchronized to a global clock also reduces the max. frequency. We are talking at about 25+x MHz for our design here.
What I'm trying to tell is, that you'd better have a really good reason to go through this and that you'd better have a team (!) to figure out which platform fulfills your needs, rather than relying on some public comments that range from any multimedia FPGA kit to outdated and low-end Spartan 3s.
But just in case you really want this, here are some companies that produce these systems (incomplete list; just what I currently remember):
* Synopsys HAPS, Synopsys ZeBu (formerly from Eve)
I agree with Lars here. The requirements that you have mentioned cannot be accommodated in a single FPGA.
I would suggest that you first try to test a subset of your design (say something involving 100 8-bit ALUs). I believe you would have already tested the correctness of your logic and design in simulation. You could then target this on an FPGA development board with a Xilinx Virtex-7 or an Altera StratixV, and evaluate if the performance/function that you are trying to achieve through your design of mesh-connected 8-bit ALUs can be really achieved.
If the performance benefit is significant, then you may start thinking about a multi-FPGA system. Till the time that you are absolutely convinced that an FPGA implementation is really going to help you, there is no point in investing such a huge amount of money.
That FPGA has 5720 6-input LUTs. How can you implement 500.000 8-bit ALUs (did you read the question?) in 5720 LUTs? That would mean you have to implement 88 ALUs in a single LUT. That sounds tough to me.
In addition to your question, considering the following comment by you:
"I have asked this question in order to estimate the budget of the project that I want to work on. As far as I know, the logic count varies from one FPGA chip to another. And so varies the cost. Therefore it will be helpful for me if I know which chip I should go for before starting the project work."
What I understood is that besides the high requirements of your design your concern at the moment is to estimate the budget.
I think making a conservative estimate is the safest, taking into account the fact that it is difficult to quantify the exact requirement of the design at the moment. Therefore, you should go for the device (available in the market) which can fit the largest of your design.