To avoid the pinholes of SiO2 from sputtering, the minimum thickness should be more than 100 nm.

Kindly optimise the thickness of layer separately on cu surface as there are variation in growth mechanism which may lead to pin holes in layer. This will be the region of leakage of current as that area will be filled in deposition of cu top layer and fine filament will destroy the purpose.

I sputtered 300 nm SiO2 on Nb without observing any pin-hole or adhesion issues. If you break vacuum before the SiO2 deposition, I would recommend a brief ion etch. This thickness was chosen for more for the microstrip design than avoiding pin-holes, so I would agree with Xuhua Wang 100 nm as a starting minimum thickness.