An FPGA compilers report clock period by analyzing all clock paths between clock-triggered devices (FFs, ROMs, RAMs etc.) but they also report clock period when there is no proper clock path due to having a single clock triggered device (FF etc) at either input or output. What is that clock period in this particular case?
Hello
If you are implementing a design on an FPGA the design is stored in the LUTs which means a specified delay from the input excitation to the generation of the output whether it is to the output flip-flop or it is connected directly to a IO. In these cases the clock also depends on the propagation delay of the signal which you can optimize by choosing an optimized routing of the configurable interconnects. The reports generated are then sum of the LUT delays and the propagation delays. Hope this is helpful.
clock period consideration to be taken after place and route. the tool calculates all the possible route from it it and selects the min clock period. u can write ur sdf file and required path after essential place and route.
FPGAs are not really the best choice for designs that don't use the clock as such, or with only a FF at start/input and end/output. The whole of digital design is built upon using the clock, but if you manage to not use it, then you would need to calculate your delay from adding up all the delays of the LUTs, plus all the routing delays on your critical path (the path through your design that is the longest and determines performance).
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