Nazar Abbas Saqib

2 Questions 2 Answers 0 Followers

Questions related from Nazar Abbas Saqib

What is the correct clock period when there is no proper clock path b/w two FFs and only a single FF exist either at input or at output in FPGAs?

An FPGA compilers report clock period by analyzing all clock paths between clock-triggered devices (FFs, ROMs, RAMs etc.) but they also report clock period when there is no proper clock path due...

01 May 2015 3,368 3 View

When you implement shift operations in FPGAs, does it allocate some hardware resources?

Hardware resources like look-up table etc

14 February 2015 7,409 2 View