Hi Pooya,

The best solution is designing a PCB layout, in which the parasitic inductances have been minimized as best as possible. But since in your case the PCB has already been designed:

As far as I know, the main function of the miller clamp capability is to avoid unintentional turning on of a switch during turning on of another switch in a leg configuration (this is often called "cross talking"). A cross talking causes shoot through and destruction of switches (at the very least, it causes unwanted switching losses). The miller clamp capability ensures that during the off times, the switch gate voltage remains below the threshold voltage in order to avoid the shoot through. I doubt that it can alleviate the voltage spikes you are looking to suppress.

A snubber can be effective in reducing the spikes. You can also try increasing the gate resistor in order to slow down the switching transitions; that also leads to less voltage spikes. But bear in mind that both of these solutions come with a cost: increased switching losses!

increase the deadtime between complimentary pulses. if the problem exists and you see ringing between D & S, then add RC snubber.

miller clamp is to avoid pulling up the gate signal during turning off.

Ali Shahabi Hani Vahedi thanks for your response.

It seems that both phenomena exist at the same time (spike leads to unwanted turn on) and they exacerbate each other.

Deadtime does not help to solve the spike problem, although it is effective in preventing the shoot through from happening. What's more interesting is that the ringing frequency is so high (200 MHz) that the RC circuit does not perform its classical role as the IGBT snubber! I'm currently working on modifying the driver board and announcing the results here.

Dear Pooya,

I have faced same issue in power electronic converter experimentation and i solved it by using RC snubber in parallel with D &S. Use the capacitor in nano farad and resistor in ohms not in kilo or mega ohms.

The ringing from Drain to Source caused by many factors, (so-call parasitic) by 2 roots:

1. Ringing of Vgs is transmitted to Vds when the transitor is turned on (during turn-on time). This ringing is cause by parasitic of RLC resonant circuit of gate driver (R is Gate resistance, L is parasitic from PCB from Driver to Gate of transistor and C is Cgate).

To reduce this effect. The only one way is to reduce the ringing of Vgs by increasing increase Rgate of the driver (to achieve over-damping).

2. Ringing of Vds cause by the RLC resonant circuit which consists of: Ron of transitor, L parasitic at Drain or Source of transistor (and package - wirebonding, also PCB) and Coss of the low-side transitor (when the low side transitor is turned-off, we can simplify it as Coss).

To reduce it, again we should use Resonant RLC circuit properties. Because you finished the PCB design, so reducing L parasitics and Coss is impossible. Of couse Ron of transistor is also a constant, so what should we do?

+ Reduce the high frequency stimulus which stimulate this RLC circuit by reducing the dv/dt rate of Vds. Of course, we can do it by increasing Rgate of driver to turn the transistor more slower. Again, this also reduce the ringing at Vgs of transitor as mentioned above. however, this also reduce the power efficiency as the switching loss increases. This method is also used to avoid the turn-on miller as dVds/dt is lower, so that the induced Vgs is much lower than threshold voltage. Again, this slower turn-on will reduce the power efficiency.

+ Use snubber circuit. This method is also based on the characteristics of RLC resonant circuit. By using RC snubber, we increase the R to achieve over-damping.

Hope it helps! Cheer!

You have parallel Fets connected. That requires a special techniques. 1) Separate resistor on each gate. 2) Additional common resistor at 10% of those on the gate, 3)separate RC snubber on each mosfet. 4) + and - of the bridge power - tightly coupled by film capacitors, right at the legs of mosfets, eg. drain top - source bottom. 5) for a very high frequency - additional ferrite bead is series with individual gate resistors (that is really optional). 6) For high voltages and currents, use isolated gate drivers (top and bottom). 7) gate driver MUST have least impedance loop gate -source. And the real solution - isolated separate drivers for each mosfet :-) . Silicone Labs does the job perfectly! AND - why 2 in parallel? For your design - 1 is more than enough! Most of your losses are - switching losses, 1 mosfet will be more efficient in your case than 2!