What are the thicknesses of each of metal layer 1 to metal layer 6 in 180 nm CMOS Ip6M? Also what are the thicknesses of each of the oxide layer separating them and the silicon layer at the end? What is the thickness of the passivization layer on top? Also kindly provide the source of information.
Just a hint: it would be beneficial if you also specify the foundry.
In general, this kind of information the foundry should provide.
Normally, foundry should provide data. Variation is from 0.1um to 6.0um per metal layer. Thinnest layers are for image sensors, thickest for RF technologies. Typical value for lower metals is say 0.3um per layer, embedded in 0.6um dielectric. Silicon wafers are typically back-grinded to 200-250um thickness. Spread of silicon thickness is also large, from 7um to 760um - depending on back-grinding option.
- Badges
- Science topic
- Similar topics
- Chemistry
- Nanotechnology
- Nanostructures
- Thin Films