This depends on what technology you are using. Generally you will get a PDK for the technology from the foundry that you will be working with. This would provide you with all the libraries for simulation, layout, and verification.

Usually the foundry you are working with will provide a PDK that will include everything that you need to do simulation layout and verification. What technology are you working with?

45nm

I hope it is sufficient enough. However, please remember that the gpdk library is provided by the Cadence to understand the design flow using cadence tools. So, please get the foundry design kit from foundries like UMC, TSMC etc.

Thank you Timir and Dr. Sivanantham for your valuable reply.

While registering in Faraday eService for downloading UMC Library, it asks for choosing one of many process libraries like (Low Power RVT/LVT/HVT, Low Leakage RVT/LVT/HVT, Standard Performance Process). Which One I should choose ? 

you generate symbols from your own generated schematics and use them for project work or sequential circuit design. in this way you can generate your own library and use it. other wise you should work on rc tool for digital design.

Hello Sandeep,

           There are different category of MOS that UMC supports. It's all depends on your application and performance requirement. Ex: If you are concerned about reducing supply voltage in any of your application then LVT is preferred. You can always refer to their fab documents before picking any device. RVT/LVT/HVT are regular, low and high threshold voltage devices. If I am not wrong then UMC's SP (standard performance) fab facilities are for commercial application and they provide mini-ASICS services for LL (low-leakage) process. You can contact them for further details.

can we get 180nm TSMC for university use?