I am unable to find much about this, can anybody give me some references as well?
You may want to read about energy-delay product of a circuit and find papers related to this metric.
Clock distribution topologies are known as one of the main limits in high-speed VLSI design. Layout considerations in VLSI circuits are also important. You can search for these topics.
Leakage current is one of the most important issues into low power VLSI design, and is getting more and more important as the technology node is increasing. In older technolgies the static power consumption in CMOS circuits was not a much important matter, but in deep submicron technologies the higher static power consumption due to leakage currents becomes a critical issue. Lot of publications have appeared in the last years about leakage current reduction.
In general, not just low power design, the effects of the technology mismatch has also got relevance because of the technology pitch reduction. In recent past, mismatching was not a very important issue for digital CMOS circuits (as difference with analog design), but nowadays, DfM (design for manufacturing) techinques are also used for digital CMOS VLSI circuits.
With scaling of the technology, survey show that leakage current is nearly equal to that of the dynamic . Hence the leakage power is of concern with the scaling of transistors. Clocking or clock distribution is another factor. As said by other researchers, a survey of papers will give right inputs.
MOSFET threshold voltage is one of the key points in low-power VLSI design. One should consider carefully whether their circuits are desired to operate below or above the threshold (partially or full) voltage.
For sense, you may want a differential amplifier topology to operate in low power, and you may use power gating, i.e. controlled switches at the head or the tail. Operating with low power (i.e. low VDD), and adding an extra switch for lower power consumption may yield your mirror devices (or less likely, load devices) to operate close or under the threshold voltage, which is a whole another topology that would not be exactly desired in this case. 'Sub-threshold' based operations on the other hand, is yet another low-power VLSI design consideration.
http://www.eeherald.com/section/design-guide/Low-Power-VLSI-Design.html
http://www.informit.com/articles/article.aspx?p=27212&seqNum=3
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