Hello, I have made a hybrid logic gate circuit in OrCAD that consists of pmos and sets. The pmos paramterers are W/L=100nm/60nm. I want to lower the dimensions of the pmos. Can you tell me what should I care for? For example, must I change also Vth or Cox? Or I can simple lower W and L while keeping the W/L ratio intact? Any thoughts are much appreciated.
You can use smaller mosfet directly instead of using larger mosfet and then reduce its dimension. For eg: use 32nm or 22 nm mosfet.
I am not familiar with the commercial models. Can you propose any to me? Thank you!
I found what I need in your publications! Thank you very much, kind sir.
Reduce the dimensions and maintain the W/L ratio. SET is a small device and you should choose smaller MOSFET for hybrid CMOSFET-SET based logic circuit design.
Hmmm indeed. The problem now that I found a mosfet, is that in PSpice I cannot simulate it successfully. It turns out that the empty transistors MbreakP and MbreakN in the breakout library of PSpice can simulate transistor up to level 9. And the smaller transistor I want to use is level 54. Do you know if there is another "empty" transistor in this library which I can use to simulate level 54 MOSFET successfully?
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