I hear that 100µm square PADs commonly used for VLSI design introduces a typical capacitance of about 5 pF (for sure it depends to many specific cases of packages). And a wire bonding used for ASIC packaging can introduce an inductance as high as 10 nH (25 nm diameter, few mm long). Have you any pieces of informations, measurements about this parasitic I/O impedances that we can anticipate at the interfaces of an IC die? My concern is for 130-350 nm ASIC technologies and for DC to tens of MHz analog applications.