Since sometimes we don't have layout drawing tool for the given technology node (say 22 nm or 16 nm) .
And also it is very difficult to draw layout to determine these capacitance especially when we only concentrate on spice simulation of the circuit. Is there any analytical method
I would think that if you know the array size, you can do an estimate of the bit line and word line lengths. You can assume minimum width.
Now a days lot of tools available for layout design. you can try using Tanner.
Sayeed
I have a reference (see below) that you will find very helpful! It allows you to estimate routing capacitance of a wire or bus before you layout your design. The algorithm can be easily captured in excel spread-sheet (see sample attached). This reference came to my knowledge from a very experienced circuit designer. I have compared the results from this reference with an EM tool and the results were reasonably close.You can verify the results from this model against Cadence's parasitic extraction (PCX) tool. This model is for capacitance only. For resistance, use the R/square co-efficient from your PDK document.
J. H. Chern, “Multilevel Metal Capacitance Models for CAD Design Synthesis Systems,” IEEE Electron Device Letters, Vol. 13, No. 1, Januaray 1992.
Thanks Mr. Harsh
What do u mean 'technology file'. Does it provide what u say
I am using PTM high performance 22 nm model
Thanks Imran sir
As far as the SRAM bitcell is concerned, what i think, the capacitance due to access transistor will dominate over the metal line(BL/BLB) capacitance. so in this regard what should we take the value of capacitance at bitlines during spice simulation
I agree with dr. Sayeed ahmed . In my work i estimate the access transistor capacitance seen by the bit line about 2fF and the total capacitance equal to number of raws multiplied by 2fF. In this case the parasitic capacitance between the Bit lines has been Ignored.
Dear Ahmed Shaaban Dessouki sir
can u provide some detail that how you estimate the access transistor capacitance seen by the bit line
I would still stay that interconnects play very important role for the sub-nano technologies.
for 130nm wire cap (only) may be 8-10% of the total cap (extracted CC+C of actual layout) while this goes up to 30% for down technologies. (depends on the technology you use).
So it is OK to ignore wire caps on BL/WL if you are on higher techno nodes, but very important when you start talking below 65nm.
Such information will be available if you have PDK of a commercial technology.
Please refer to the book in Title: CMOS VLSI Design: A Circuits and Systems perspective
By: Neil E. Weste and David M. Harris
Chapter 2 and 4
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