This has been bothering me for a while.
In some of the design notes of power management ICs , it is mentioned that peak current mode control has 'lower gain - wider bandwidth' inner loop compared to that of average current mode control. Why is it so?
Quote from a design note-
"Peak current mode control has a low gain, wide bandwidth current loop which generally makes it unsuitable for a high performance power factor corrector since there is a significant error between the program signal and the current."
Thanks