Siddhartha,

would you please explain the operation of the given circuit in the figure?

I could not see how it works as a source follower. Source follower means that the source follows the gate voltage. So, one would take the output from the emitter and put a low pass filter at the output. One can put also low pass filter at the input to realize low ripple input voltage at the drain and the ground. The gate source must be controlled by PWM rectangular waveform which must be strong enough to on the transistor.

This must be the circuit configuration in order to work as SMPS.

Best wishes

Abdelhalim abdelnaby Zekry , Thank you for the reply.

Strictly speaking, it is right that the configuration cannot be termed as a source-follower. The circuit configuration is popularly known as a "capacitance multiplier", which again is another misnomer.

My intention with this circuit is to implement a low pass filter with very low corner frequency. Again, since the filter is intended for use with a power supply (and not signal), the resistsors are necessarily expected to be low as higher values of R would limit the maximum load current of the PS unit. However with very low values of R, the values of C would be ridiculously low.

In this circuit, the filer is connected to the Gate of the MOSFET, so the filtered voltage would drive the Gate yet the On-state R_DS of the MOSFET would still be low which would hardly limit the load current of the power supply unit.

Again, since the current to be delivered to the Gate-Source terminals would be much lower than I_DS, the values of R in the filter can be high and values of C can thus be smaller making it a compact circuit.

The simulations showed promising results, yet results of practical implementation were horrible. So, I just wanted to know where I was going wrong.

Yes the circuit is now more clear. It must function as a source follower, so if the vG is constant free of ripple the output voltage will be free of ripples. In fact the small signal gain of this circuit must be smaller than one. So if the ripple at the gate of the mos transistor is reduced because of the filter, the ripples at the output must be reduced accordingly.

What is the load resistance between the source and the ground.

As a test you disconnect the gate and measure the ripple at C2.

The second point is that what is value of VDS=?

In order to operate in the voltage follower mode the transistor must be in the active mode. So, you have to connect a suitable resistance at the output.

You have to take care of the ripple frequency. As it increases it will be attenuated by the filter.

Best wishes

The input voltage is 24V and I intend to have a load current of 2A, which makes the load resistance about 12 Ohms. However, it so happens that due to attenuation of the filter, I manage to get an output of about 20 somethign volts at the load and 1.5-1.6 A.

The power supply that I wish to use this filter with is a SMPS, and we managed to measure the ripple which is about 200mV(p-p), the ripple component looks like square pulses with fundamental frequency of about 50Hz. I plugged in those data into my simulation model and the ripple that I get at the output in the simulation is about 100uV(p-p), with a square wave-shape, in phase with the input ripple, at steady state. However, in the actual prototype circuit the ripple just remains the same, no practical attenuation whatsoever.

You mention ripple at 50Hz from a SMPS . . . do you mean 50kHz?

This circuit has poor load regulation and is also dependent upon a low source impedance for your input power. Have you simulated the input source impedance, short-term drops in input voltage, and variations in the output load? Can you share your full simulation circuit? Do you have specifications you are trying to meet? Understanding your goals would help with our analysis.

Carl Van Wormer, strangely though, but we observed the ripple to be at 50Hz square pulses on the oscilloscope. Nevertheless, with the filter I was willing to accommodate for typical high frequency ripples of SMPS units too.

I've enclosed the simulation file. It is true that the load regulation is horrible for this circuit. At full load, the output voltage drops down by 5v. I had planned to look into the issue once I could validate atleast the ripple attenuation results with that of the simulation results.

Our objective is to design a filter for a power supply unit that currently has a ripple of about 200mV(p-p) so as to ensure that the output has a ripple of not more than 5mv(p-p). The power supply unit has an output voltage of 24V and full load current of 2A.

I don not have MultiSim, so I can't see your simulations. I use LTspice for my work, and can provide my simulation circuits if you have LTspice. The FET Drain is connected to the same DC input voltage as the Gate and the Source follower function gives the output voltage to the load to satisfy the Drain current - vs. - Gate-Source curves. The DC transfer function is based on the slope of those curves and gives you relatively poor regulation. Multiple copies of this design will have significant device dependent output voltage variations since the threshold voltage (Vgs) is not a tightly controlled parameter and will also have temperature related drifts.

If your operating parameters are not critical you may be able to add more parts to make this circuit work "good enough" for your prototype, but it should not be the basis for a product. There are many power supply circuits that could be designed for your goals, but you have not given enough information about your original voltage source circuit or your line/load regulation requirements to make good re-design suggestions.

Use simple a L-C filtering with a cutoff frequency 5-10 times greater than your converter's crossover frequency

I don't really see a point in this design as it is going to have rather high minimal dropout (as high as threshold gate voltage). It is ~4V for this MOSFET.

In the old times BJT based 'smoothing' circuits like that were used (BJT kind of has just 0.7V 'threshold' but needs some base current).

Now, there are several specialized chips to build LDO using MOSFET, e.g.

http://ww1.microchip.com/downloads/en/DeviceDoc/mic5156.pdf