how to solve this error in VHDL code?

07 October 2017 1 4K Report

any one can tell me how to solve this error...

code and simulation is OK and output of simulation is ok without any error but when i try to implemented the design the error come to me(open attached file)

Abdelhalim abdelnaby Zekry

Please connect with Dr. Reem. You know her. She is an expert in VHDL and its implementation on FPGA.

Best wishes

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