Are you really considering Volts (eV probably, I guess) or rather Millivolts (meV) ?!

It is V(volt) not mV 

How do you know the Dirac point has moved there? This amounts to about three times the occupied valence band width!! I cannot imagine this result to be true...

Quite generally I would have said that since the vicinity of the Dirac point has very little DOS, making contacts almost inevitably will dope the material (little charge transfer suffices to shift the Fermi level away from the DPs). That is already true for graphite (there exists relevant literature with adsorbed metals on graphite, for example, clearly indicating shifts of the order of a fraction of an eV).

The details of the experiment is as follows: I had Si(100 n+ doped) wafer, I grew 330 nm Silicon dioxide(wet oxidation). I needed around 300nm oxide thickness, so I did buffered HF etching of oxide, I got thickness around 290nm. This was good enough to view graphene under optical microscope.then I transferred graphene on SiO2 substrate using mechanical exfoliation of HOPG. used ebl for making contacts to the devices. After lift-off I did electrical measurements, IV curve showed minimum conductivity point (Dirac point) to be at 80V.

  Transfer characteristics is attached

I have to admit I'm neither an expert in graphene preparation nor in transport measurements. I do have knowledge about electronic structure, though.

Would you mind providing a rough sketch of the measurement set-up? Is it a four probe technique? I would think that is mandatory to eliminate contributions owing to contact resistances. And 80V is a priori the voltage across your sample. How do you associate the location in k-space where transport occurs with that voltage? This doesn't sound intuitive to me.

(btw. you're putting quite some power in that flake, don't you?! What does the temperature of the flake do under these circumstances? The heat capacity of such a flake won't be very large, will it ?!)

In the following words, NP(conductive neutral point) means DP that mentioned above. I think NP is more reasonable name for the gate voltage that lets fermi level lying on DP in K-space.

To Scdc dc

It is normal that NP is located at positive voltage due to P type doping introduced by ploymer residues and molecules(H2O&O2) adsorption. 

Based on your work I have two suggestions to you: one is testing your devices under vacuum and to implement soft bake before test. the other one is change your silicon doping type to P++.

This may shift NP to 0V  but it is next to impossible to restore NP to 0V.

To Kai Fauth

In my experience, Scdc dc used three probes to test the graphene device: Gate Source and Drain. The voltage between Drain and source is constant value(2V) and gate voltage sweeps from ~0V to 150V. 

When the gate voltage is 80V, in the device the fermi level(Ef) is placed at DP.Actually the variation of Ef when changing gate voltage from 0 to 80V is small as you mentioned. But the most voltage drops on the gate capacitance. Furthermore the gate capacitance is small due to the thick SiO2 layer(290nm). So it is reasonable that gate voltage needs so large voltage.

For the same graphene device if we reduce the dielectric layer from 290nm to 145nm the NP will lies at ~40V. The voltage we achieved from testing changes but the variation of Ef doesn't change.

to Kunpeng Jia

Thanks for your answer.

As you said it was three probe measurement setup.

What difference does it make if we use P++ wafers instead of n++?

Dawuth Pathan,

The Ef position of gate material will affect graphene doping level.

The image that higher Ef of gate material attracts more electron into graphene channel.

You can reference MIS structure analysis in traditional semiconductors.  

Kunpeng Jia,

If I use p++ doped Si as backgate then effective workfunction of Si will be approximately =electron affinity of Si + EG of Si =>  Workfunction will be 4.05+1.1 =5.15 eV.

intrinsic Graphene(without any doping) work function is approximately same as graphite ~4.6eV. 

This shows that after we make SI/SiO2/Graphene structure, graphene will be p doped (because of lower work function of graphene)

already our graphene is being doped p-type because of H2O/O2 and resist residues, that means work function of graphene is increasing because of p doping.

If we use p++ Si, and if its workfucntion is lower than that of p doped graphene, it will reduce effective p-doping of graphene.

I am right?

but then In that case n++ wafer will help more as compared to p++ wafer

Hello Dear,

Shifting of dirac point is happened in Graphene base devices.I am also working on GFET and I also faced the same.There may be many reasons we need to understand first, before how to restore it towards zero.

1.In GFET dirac point shifting is channel length dependent, for short channel the dirac pont shifts towrds the left and for long it shifts towards the right.And the length needs to optimized for the same.

2.Secondly, the fabrication process needs to be optimized for the same.As the presence of moisture contents in the Graphene active area shifts the dirac towards right(as the moisture added some extra electrons into the active area)

3.More importantly the dirac may be the function of the applied bias volatge(Vds for GFET case),as increase in the Vds shfits the dirac point towards right and decrease in Vds shifts towrds left.

Hope dear Pathan it will works for you for more details,plz go for the attached files.

Good day & Take care!!!