Dear Zhe,

It is my pleasure that you invited me to give you a reply to your interesting question.

At first you can directly measure the leakage gate current directly.

So that you get sure of the leakage.

There are some sources of leakage current between drain and gate:

It can be that the oxide layer is structurally defective such that pinholes in which the metal can penetrate and makes microshorts in the oxide layer itself.

It can due to overlapping of the gate tantalization towards the drain.

There may be weak pints in the oxide that it early breakdowns at smaller voltage across the insulator layer.

If the later is very thin there will be probability of conduction by tunneling.

You can examine your oxide layer under the microscope and the methods of thermal topography.

Best wishes

Abdelhalim abdelnaby Zekry Would you like to give me some suggestions? Thank you very much! I feel that the most important issue is not the gate leakage current, instead, the positive Ids current in p-type transistor means that my semiconductor is not working so I only detected gate leakage current. Do you think I am thinking in the right angle? Thank you very much!

Dear Zhe Sue

We very often tested P3HT organic transistors using various substrates and dielectrics. What device structure do you use? In particular the dielectrics play an important role.

Dear Zhe,

It is my pleasure that you invited me to give you a reply to your interesting question.

At first you can directly measure the leakage gate current directly.

So that you get sure of the leakage.

There are some sources of leakage current between drain and gate:

It can be that the oxide layer is structurally defective such that pinholes in which the metal can penetrate and makes microshorts in the oxide layer itself.

It can due to overlapping of the gate tantalization towards the drain.

There may be weak pints in the oxide that it early breakdowns at smaller voltage across the insulator layer.

If the later is very thin there will be probability of conduction by tunneling.

You can examine your oxide layer under the microscope and the methods of thermal topography.

Best wishes

Two tunneling mechanisms are responsible for the gate leakage, Fowler-Nordheim tunneling and direct tunneling. The gate leakage increases exponentially as the dielectric thickness is reduced. On the other hand, a thin gate dielectric reduces the short-channel effect and improves the driving capabilities of a transistor. However, a tradeoff between this is necessary. Material with high dielectric constant can be used with reduced thickness for better result.

Xuhua Wang Thank you for answering my question! We used ion gel as dielectric and CNT as electrodes. I heard some suggestions that the positive Ids in my P3HT based transistors is not the actual Ids and it is the gate leakage current. This means that no current through our P3HT layer. Would you like to give me some suggestions that why this happens and how to solve this? Thank you very much!

Abdelhalim abdelnaby Zekry Thank you very much for answering my question! Sorry I did not mention the material I used. I used ion gel instead of SiO2 as a dielectric layer in my transistor. In that case, do you think some other factors will influence my transistor and cause no current through the P3HT layer, so I only get gate leakage current in my Ids? Thank you very much!

You must stop gate leakage in order to be able to build control charges on the gate electrode. When you have partial shorts as i said before then you can not get the field effect as one loses the control on the gate electrode.

You must be systematic and make some investigations by your self to get out what is the real cause for such current leakage.

If you display the I-V characteristics one can give more specific answer.

I listed the causes of leakage before and gave you some hints to proceed.

What about the operation with SiO2?? is it a normal operation???

Best wishes

Abdelhalim abdelnaby Zekry Thank you for answering me! When we use SiO2 as a dielectric layer and Au as electrodes, the operation is normal.

Dear Zhe Su,

The followings paper could help you to explain why the leakage current is high using ion gel as dielectric for your organic transistors. I copy the part of their explanations to help you for your work.

"Hysteresis and leakage were challenges in the ion gel gated OTFT preparation. The ionic liquid is hygroscopic, making the gel susceptible to water impurities. The impurities can cause leakage and hysteresis due to electrochemical reactions at the electrodes even at low voltages. "

The paper link is in the following

https://trepo.tuni.fi/handle/123456789/20899

Dielectric permittivity, thickness, structural composition and S-D spacing are key factors to control leakage.

From my experience, the most reliable structure with reproducible minimum gate leakage for OFET transistors and metal-insulator-semiconductor (MIS) structures is Benzocyclobutene (BCB) passivated (20 nm) SiO2 (200-300 nm) on degenerated p+ or n+ Si, which serves as the gate electrode.

Dear Zhe

The leakage current in the gate oxide is calculated by using the Fowler Nordheim (FN) tunneling equation, where non-local dielectric- and dielectric-Semiconductor tunneling is represented by a non-local mesh construction.

A gate oxide with a high relative permittivity notably improves the transistor performance. However, an increased gate leakage current is calculated. this fact is due to the reduced ΔEC which originates in the MOS structure. Although a thicker oxide layer (SiO2) limits the leakage currents showing however undesired detrimental effects on the device on-state figures of merit (e.g. Vth shift and gm drop), as an useful compromise in overcoming this design issue a dielectric stack structure where an interfacial layer with a large conduction band offset inserted at the interface. For example, by assuming a 2 nm thick SiO2 interfacial layer in the HfO2/SiO2/ Semiconductor.

Please find enclosed a relevant paper .

Regards

Hichem Bencherif