I am working on SRAM memory cell and doing process analysis through Monte Carlo simulation by varying threshold voltage variation. I want to measure leakage current of the memory cell at different runs.
My problems are;
How we can model threshold voltage variation in Hspice.
How to measure leakage power.
The leakage power can be measured from the gate oxide leakage current (Measure/print/plot gate current) and subthreshold leakage currents. Regarding the threshold voltage variation modeling, there are some papers available for your reference:
http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.10.9393&rep=rep1&type=pdf
http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.167.8818&rep=rep1&type=pdf
sir please tell me how to find leakage power dissipation of 6TSRAM cell by simulation method on cadence.
Leakage power is the power which is comsumed in sram cell during hold mode. During hold time WL singhal is off while BL and BLB are precharged to VDD. It should be noted that no transition activity activity happen during hold mode.
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