Hello dear Jeph Daligdig

The answers to your question can be different depending on the properties of the CMOS process.

In an n-well CMOS process (a single-well n-well process), the substrate is p-type, which is the shared body (bulk) of all nMOS transistors. In such a case, an n-channel MOSFET's bulk will - by default - be connected to the substrate, which conventionally is connected to the most negative DC potential (Ground or -VSS) to make sure all nMOS source-bulk and drain-bulk pn junctions are reverse biased (at least for static/DC cases). For those nMOS transistors whose source terminals are grounded (or connected to -VSS - if exists), "body effect" on threshold voltage is avoided, but the others inevitably suffer from it.

Considering the same case (n-well CMOS) for pMOS...

A pMOS transistor is realized in an n-well, which is also its bulk. Since an individual n-well can be made specific to a pMOS transistor, that bulk can be freely connected to any point, e.g. body-driven circuits (but of course one must make sure that the source-bulk and drain-bulk pn junctions remain reverse biased during operation). For sure, it is also possible to make a source-bulk connection to avoid body effect. If several pMOS transistors share the same n-well, their bulks are also by default connected to each other. Usually, the most preferred method in such a case is to connect the n-well to to the most positive DC potential (VDD), to guarantee keeping the source-bulk and drain-bulk pn junctions of the pMOSTs reverse biased during operation.

In a p-well process (is preferred less), the nMOS transistors can have their own p-well or can share the same p-well (Same facilities as those of a pMOS in an n-well process), while all pMOSTs share the same bulk (n-type substrate).

For the case of multiple-well technologies (e.g. twin-well), both n-well and p-well facilities are available, which avail independent well possibility (and/or source-bulk shorting - if preferred) for both nMOS and pMOS transistors.

Best regards...

NOTE#1: Because the substrate (or a large well) is distributed over a large area, the assumed body region (let's assume it as the region under the gate oxide and below/around the drain & source regions) of a transistor may be distant from the "good" electrical body contact ("substrate contact" or "well contact"), which - due to the relatively lower electrical conductivity of the substrate/well region - can create a large series body terminal resistance. To avoid this and some other undesired problems (e.g. "latch-up") as far as possible, it may be wiser to put as many substrate/well contacts as possible close to each transistor, which otherwise may suffer from the mentioned problems.

NOTE#2: Using an independent well for a transistor (or more transistors, e.g. differential pair) is at the cost of increasing the consumed chip area and may also increase some parasitic capacitances, thus delay, as well. Therefore, it should be used only for those transistors which can make use of this facility to improve some performance behavior.

If you are working on a cadence virtuoso eda tool then select body type and choose either integrated or detached as per designs requirement.