we have designed a proposed multiplier using Verilog HDL code. Now we want to apply our proposed multiplier for image processing applications. We need procedure or steps or example codes. Can anyone help us to implement?
Dear Bala Murugan s
The image compression using DCT may be taken as a problem .
8X8 block of image stored as array , and the algorithm of DCT with available multiplier core vs proposed multiplier may be compared in term of processing time and resource utilization.
I have found the similar threads (but with answers/solutions).
The following links I found useful for your case:
https://www.researchgate.net/post/How_can_I_read_an_image_as_a_text_file_in_Verilog_HDL
https://www.quora.com/How-do-I-do-image-processing-using-Verilog-on-FPGA
Dear Bala Murugan s,
Any matrix process involves multiplier. you can implement your code for DCT based Image Compression(JPEG) and wavelet based compression
I have already explained the process in following thread. please have a look:
https://www.researchgate.net/post/How_can_I_read_an_image_as_a_text_file_in_Verilog_HDL
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