The parasitic capacitances extracted according to how your layout is designed might be critical in affecting the actual performance of your design.  In order to get an idea of how the design would work from your layout, you should perform a post-layout simulation from the extracted view.  The procedure is identical to that for simulating from the schematic view. So this helps you to get idea about how much deviation you're getting from both the results. General tolerance of 5% is accepted. If both pre and post matches exactly(or with the tolerance) than you're good to go.

very important..... the post layout simulations will show real working of chip (very near to fabricated chip). it includes all pvt, wire load models, inter-connect effects and parasitics.

Thanks dear Saurav and Jagdeep for your valuable response..

In circuit design one assumes ideally conducting wires and thereby one neglects their resistance and capacitance. It is so that these wires occupy a large portion of the chip area may be as high as 40 percent. In such micro structures as in integrated circuit chips these parasitic elements can make appreciable change in the dynamic response of the circuit especially at high operating clock frequencies.

So, in order to verify the operation of the circuit under real operating condition and before the the fabrication it is required to make post lay out simulation.

Best wishes